AD7943/AD7945/AD7948
REV. B –7
ORDERING GUIDE
Temperature Linearity Nominal Package
Model Range Error (LSBs) Supply Voltage Option
1
AD7943BN –40°C to +85°C ±0.5 +5 V N-16
AD7943BR –40°C to +85°C ±0.5 +5 V R-16
AD7943BRS –40°C to +85°C ±0.5 +5 V RS-20
AD7943AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-16
AD7943ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20
AD7945BN –40°C to +85°C ±0.5 +5 V N-20
AD7945BR –40°C to +85°C ±0.5 +5 V R-20
AD7945BRS –40°C to +85°C ±0.5 +5 V RS-20
AD7945AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-20
AD7945ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20
AD7945TQ –55°C to +125°C ±1 +5 V Q-20
AD7948BN –40°C to +85°C ±0.5 +5 V N-20
AD7948BR –40°C to +85°C ±0.5 +5 V R-20
AD7948BRS –40°C to +85°C ±0.5 +5 V RS-20
AD7948AN-B –40°C to +85°C ±1 +3.3 V to +5 V N-20
AD7948ARS-B –40°C to +85°C ±1 +3.3 V to +5 V RS-20
NOTE
1
N = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
I
OUT1
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
I
OUT2
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to V
DD
+ 0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . ±10 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 670 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, Soldering, (10 sec) . . . . . . . . . . +260°C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 132°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD7943/AD7945/AD7948
REV. B–8–
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in Least Significant Bits or as a percentage of full-
scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after offset error has been adjusted out and is ex-
pressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage Current
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the I
OUT1
terminal,
it can be measured by loading all 0s to the DAC and measuring
the I
OUT1
current. Minimum current will flow in the I
OUT2
line
when the DAC is loaded with all 1s.
Output Capacitance
This is the capacitance from the I
OUT1
pin to AGND.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified both with the AD843 as the output op amp in the
normal current mode and with the AD820 in the biased current
mode.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-s. It is measured with the reference input connected
to AGND and the digital inputs toggled between all 1s and all
0s. As with Settling Time, it is specified with both the AD817
and the AD820.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I
OUT1
terminal, when all 0s are
loaded in the DAC.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the I
OUT1
pin and subsequently on
the op amp output. This noise is digital feedthrough.
PIN CONFIGURATIONS
DIP/SOP SSOP DIP/SOP/SSOP DIP/SOP/SSOP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
(Not to Scale)
AD7945
DB5
DB6
DB7
AGND
DGND
DB11
DB8
DB9
DB10
DB4
DB3
DB2
V
REF
V
DD
WR
DB1
DB0
CS
I
OUT1
R
FB
TOP VIEW
(Not to Scale)
AD7943
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
I
OUT1
I
OUT2
AGND
STB1
LD1
SRO
SRI
STB2
R
FB
V
REF
V
DD
CLR
DGND
STB4
STB3
LD2
TOP VIEW
(Not to Scale)
AD7943
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC = NO CONNECT
STB2
SRI
SRO
I
OUT2
AGND
STB1
LD1
NC
NC
LD2
STB3
STB4
V
REF
V
DD
CLR
DGND
NC
NC
I
OUT1
R
FB
TOP VIEW
(Not to Scale)
AD7948
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DB4
DB5
DB6
AGND
DGND
CSMSB
DB7 (MSB)
CTRL
DF/DOR
DB3
DB2
DB1
V
REF
V
DD
WR
DB0 (LSB)
LDAC
CSLSB
I
OUT1
R
FB
AD7943/AD7945/AD7948
REV. B –9
AD7943 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
I
OUT1
DAC current output terminal 1.
I
OUT2
DAC current output terminal 2. This should be connected to the AGND pin.
AGND This pin connects to the back gates of the current steering switches. In normal operation, it should be connected
to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between
0 V and the 1.23 V. See Figure 11 for more details.
STB1 This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal. STB3
must be high. STB2, STB4 must be low.
LD1, LD2 Active low inputs. When both of these are low, the DAC register is updated and the output will change to
reflect this.
SRI Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs,
when they are enabled.
STB2 This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal.
STB3 must be high. STB1, STB4 must be low.
STB3 This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1,
STB2, STB4, must be low.
STB4 This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal. STB3
must be high. STB1, STB2 must be low.
DGND Digital Ground.
CLR Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch.
V
DD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased
Mode Operation.
V
REF
DAC reference input.
R
FB
DAC feedback resistor pin.
AD7945 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
I
OUT1
DAC current output terminal 1.
AGND This pin connects to the back gates of the current steering switches. The DAC I
OUT2
terminal is also connected
internally to this point.
DGND Digital Ground.
DB11–DB0 Digital Data Inputs.
CS Active Low, Chip Select Input.
WR Active Low, Write Input.
V
DD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
V
REF
DAC reference input.
R
FB
DAC feedback resistor pin.

AD7945BR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 3.3V/5V Multiplying 12-Bit Parallel IF
Lifecycle:
New from this manufacturer.
Delivery:
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