AD7945BR Datasheet AD7945BRSZ-REEL, AD7945ARSZ-B, AD7943ARSZ-B | P13-P15

AD7943/AD7945/AD7948

REV. B –13–

GENERAL DESCRIPTION

D/A Section

The AD7943, AD7945 and AD7948 are 12-bit current-output

D/A converters. A simplified circuit diagram is shown in Fig-

ure 13. The DAC architecture is segmented. This means that

the 2 MSBs of the 12-bit data word are decoded to drive the

three switches A, B and C. The remaining 10 bits of the data

word drive the switches S0 to S9 in a standard inverting R-2R

ladder configuration.

Each of the switches A to C steers 1/4 of the total reference

current into either I

OUT1

or I

OUT2

with the remaining 1/4 of the

total current passing through the R-2R section. Switches S9 to

S0 steer binarily weighted currents into either I

OUT1

or I

OUT2

. If

OUT1

and I

OUT2

are kept at the same potential, a constant cur-

rent flows in each ladder leg, regardless of digital input code.

Thus, the input resistance seen at V

REF

is always constant. It is

equal to R/2. The V

REF

input may be driven by any reference

voltage or current, ac or dc that is within the Absolute Maxi-

mum Ratings.

The device provides access to the V

REF

, R

, and I

OUT1

termi-

nals of the DAC. This makes the device extremely versatile and

allows it to be configured in several different operating modes.

Examples of these are shown in the following sections. The

AD7943 also has a separate I

OUT2

pin. In the AD7945 and

AD7948 this is internally tied to AGND.

When an output amplifier is connected in the standard configu-

ration of Figure 14, the output voltage is given by:

OUT

= –D

REF

where D is the fractional representation of the digital word

loaded to the DAC. D can be set from 0 to 4095/4096, since it

has 12-bit resolution.

REF

R/2

RR R

CABS9S8S0

OUT1

OUT2

2R 2R 2R 2R 2R 2R

SHOWN FOR ALL 1S ON DAC

Figure 13. Simplified D/A Circuit Diagram

UNIPOLAR BINARY OPERATION

(Two-Quadrant Multiplication)

Figure 14 shows the standard unipolar binary connection dia-

gram for the AD7943, AD7945 and AD7948. When V

is an

ac signal, the circuit performs two-quadrant multiplication.

Resistors R1 and R2 allow the user to adjust the DAC gain

error. With a specified gain error of 2 LSBs over temperature,

these are not necessary in many applications. Circuit offset is

due completely to the output amplifier offset. It can be re-

moved by adjusting the amplifier offset voltage. Alternatively,

choosing a low offset amplifier makes this unnecessary.

A1 should be chosen to suit the application. For example, the

OP07 is ideal for very low bandwidth applications (10 kHz or

OUT1

OUT2

OUT

SIGNAL GROUND

A1: OP07

AD711

AD843

AD845

AGND

DAC

REF

R1 20V

AD7943/45/48

R2 10V

RFB

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED

WHEN USING HIGH SPEED AMPLIFIER.

Figure 14. Unipolar Binary Operation

lower) while the AD711 is suitable for medium bandwidth ap-

plications (200 kHz or lower). For high bandwidth applications

of greater than 200 kHz, the AD843 and AD847 offer very fast

settling times.

The code table for Figure 14 is shown in Table III.

Table III. Unipolar Binary Code

Digital Input Analog Output

MSB LSB (V

OUT

as Shown in Figure 14)

1111 1111 1111 –V

REF

(4095/4096)

1000 0000 0001 –V

REF

(2049/4096)

1000 0000 0000 –V

REF

(2048/4096)

0111 1111 1111 –V

REF

(2047/4096)

0000 0000 0001 –V

REF

(1/4096)

0000 0000 0000 –V

REF

(0/4096) = 0

NOTE

Nominal LSB size for the circuit of Figure 14 is given by: V

REF

(1/4096).

AD7943/AD7945/AD7948

REV. B–14–

BIPOLAR OPERATION

(Four-Quadrant Multiplication)

Figure 15 shows the standard connection diagram for bipolar

operation of the AD7943, AD7945 and AD7948. The coding is

offset binary as shown in Table IV. When V

is an ac signal,

the circuit performs four-quadrant multiplication. Resistors R1

and R2 are for gain error adjustment and are not needed in

many applications where the device gain error specifications are

adequate. To maintain the gain error specifications, resistors

R3, R4 and R5 should be ratio matched to 0.01%.

OUT1

OUT2

OUT

SIGNAL GROUND

AGND

DAC

REF

R1 20V

AD7943/45/48

R2 10V

RFB

R4 20kV

10kV

20kV

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED

WHEN USING HIGH SPEED AMPLIFIER, A1.

Figure 15. Bipolar Operation (Four-Quadrant

Multiplication)

Suitable dual amplifiers for use with Figure 15 are the OP270

(low noise, low bandwidth, 15 kHz), the AD712 (medium

bandwidth, 200 kHz) or the AD827 (wide bandwidth, 1 MHz).

Table IV. Bipolar (Offset Binary) Code

Table Digital Input Analog Output

MSB LSB (V

OUT

as Shown in Figure 15)

1111 1111 1111 +V

REF

(2047/2048)

1000 0000 0001 +V

REF

(1/2048)

1000 0000 0000 +V

REF

(0/2048) = 0

0111 1111 1111 –V

REF

(1/2048)

0000 0000 0001 –V

REF

(2047/2048)

0000 0000 0000 –V

REF

(2048/2048) = –V

REF

NOTE

Nominal LSB size for the circuit of Figure 15 is given by: V

REF

(1/2048).

SINGLE SUPPLY APPLICATIONS

The “-B” versions of the devices are specified and tested for

single supply applications. Figure 16 shows the recommended

circuit for operation with a single +5 V to +3.3 V supply. The

OUT2

and AGND terminals are biased to 1.23 V. Thus, with 0 V

applied to the V

REF

terminal, the output will go from 1.23 V (all

0s loaded to the DAC) to 2.46 V (all 1s loaded). With 2.45 V

applied to the V

REF

terminal, the output will go from 1.23 V (all

0s loaded) to 0.01 V (all 1s loaded). It is important when con-

sidering INL in a single-supply system to realize that most

single-supply amplifiers cannot sink current and maintain zero

volts at the output. In Figure 16, with V

REF

= 2.45 V the re-

quired sink current is 200 µA. The minimum output voltage

level is 10 mV. Op amps like the OP295 are capable of main-

taining this level while sinking 200 µA.

Figure 16 shows the I

OUT2

and AGND terminals being driven

by an amplifier. This is to maintain the bias voltage at 1.23 V

as the impedance seen looking into the I

OUT2

terminal changes.

This impedance is code dependent and varies from infinity (all

0s loaded in the DAC) to about 6 kΩ minimum. The AD589

has a typical output resistance of 0.6 Ω and it can be used to

drive the terminals directly. However, this will cause a typical

linearity degradation of 0.2 LSBs. If this is unacceptable then

the buffer amplifier is necessary. Figure 9 shows the typical

linearity performance of the AD7943/AD7945/AD7948 when

used as in Figure 16 with V

set at +3.3 V and V

REF

= 0 V.

OUT1

OUT2

OUT

SIGNAL GROUND

A1: OP295

AD822

OP283

AGND

DAC

REF

AD7943/45/48

RFB

+5V

5.6kV

AD589

+3.3V

DGND

Figure 16. Single Supply System

AD7943/AD7945/AD7948

REV. B –15–

MICROPROCESSOR INTERFACING

AD7943 to ADSP-2101 Interface

Figure 17 shows the AD7943 to ADSP-2101 interface diagram.

The DSP is set up for alternate inverted framing with an inter-

nally generated SCLK. TFS from the ADSP-2101 drives the

STB1 input on the AD7943. The serial word length should be

set at 12. This is done by making SLEN = 11 (1011 binary).

The SLEN field is Bits 3–0 in the SPORT control register

(0x3FF6 for SPORT0 and 0x3FF2 for SPORT1).

With the 16 MHz version of the ADSP-2101, the maximum

output SCLK is 8 MHz. The AD7943 setup and hold time of

10 ns and 25 ns mean that it is compatible with the DSP when

running at this speed.

The OUTPUT FLAG drives both LD1 and LD2 and is brought

low to update the DAC register and change the analog output.

ADSP-2101

AD7943

STB4STB2

+5V

TFS

SCLK

OUTPUT FLAG

CLR

STB3

LD1

LD2

STB1

SRI

Figure 17. AD7943 to ADSP-2101 Interface

AD7943 to DSP56001 Interface

Figure 18 shows the interface diagram for the AD7943 to the

DSP56001. The DSP56001 is configured for normal mode

synchronous operation with gated clock. The serial clock, SCK,

is set up as an output from the DSP and the serial word length

is set for 12 bits (WL0 = 1, WL1 = 0, in Control Register A).

SCK from the DSP56001 is applied to the AD7943 STB3 in-

put. Data from the DSP56000 is valid on the falling edge of

SCK and this is the edge which clocks the data into the AD7943

shift register. STB1, STB2 and STB4 are tied low on the

AD7943 to permanently enable the STB3 input.

When the 12-bit serial word has been written to the AD7943,

the LD1, LD2 inputs are brought low to update the DAC

DSP56001

AD7943

STB4STB2STB1

+5V

SCK

STD

OUTPUT FLAG

CLR

STB3

LD1

LD2

SRI

Figure 18. AD7943 to DSP56001 Interface

AD7945 to MC68000 Interface

Figure 19 shows the MC68000 interface to the AD7945. The

appropriate data is written into the DAC in one MOVE instruc-

tion to the appropriate memory location.

MC68000

ADDRESS

DECODE

AD7945

DB11 – DB0

A1 – A23

DTACK

R/W

D15 – D0

Figure 19. AD7945 to MC68000 Interface

AD7948 to Z80 Interface

Figure 20 is the interface between the AD7948 and the 8-bit

bus of the Z80 processor. Three write operations are needed to

load the DAC. The first two load the MS byte and the LS byte

and the third brings the LDAC low to update the output.

Z80

ADDRESS

DECODE

AD7948

CSMSB

DB7 – DB0

A0 – A15

MREQ

D7 – D0

CSLSB

LDAC

ADDRESS BUS

DATA BUS

Figure 20. AD7948 to Z80 Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AD7945BR

Mfr. #:

Buy AD7945BR

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 3.3V/5V Multiplying 12-Bit Parallel IF

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AD7945BR

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