OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7945BR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
AD7943/AD7945/AD7948
REV. B–4–
AC PERFORMANCE CHARACTERISTICS
NORMAL MODE
Parameter B Grades T Grade Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 600 700 ns typ To 0.01% of Full-Scale Range. V
REF
=
+10 V; DAC Latch Alternately Loaded with
All 0s and All 1s
Digital to Analog Glitch Impulse 60 60 nV-s typ Measured with V
REF
= 0 V. DAC Latch
Alternately Loaded with All 0s and All 1s
Multiplying Feedthrough Error –75 –75 dB max DAC Latch Loaded with All 0s
Output Capacitance 60 60 pF max All 1s Loaded to DAC
30 30 pF max All 0s Loaded to DAC
Digital Feedthrough (AD7943) 5 5 nV-s typ Feedthrough to the DAC Output with LD1,
LD2 High and Alternate Loading of All 0s
and All 1s into the Input Shift Register
Digital Feedthrough (AD7945, AD7948) 5 5 nV-s typ Feedthrough to the DAC Output with CS
High and Alternate Loading of All 0s and
All 1s to the DAC Bus
Total Harmonic Distortion –83 –83 dB typ
Output Noise Spectral Density
@ 1 kHz 35 35 nV/√Hz typ All 1s Loaded to DAC. V
REF
= 0 V. Output
Op Amp Is OP07
Specifications subject to change without notice.
(AD7943: V
DD
= +4.5 V to +5.5 V; V
IOUT1
= V
IOUT2
= AGND = 0 V. AD7945, AD7948: V
DD
= +4.5 V to +5.5 V; V
IOUT1
=AGND =
0 V. V
REF
= 6 V rms, 1 kHz sine wave; T
A
= T
MIN
to T
MAX
; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in-
cluded for Design Guidance and are not subject to test.
AC PERFORMANCE CHARACTERISTICS
BIASED MODE
(AD7943: V
DD
= +3 V to +5.5 V; V
IOUT1
= V
IOUT2
= AGND = 1.23 V. AD7945, AD7948: V
DD
= +3 V to +5.5 V; V
IOUT1
= AGND =
1.23 V. V
REF
= 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; T
A
= T
MIN
to T
MAX
; unless otherwise noted.) These
characteristics are included for Design Guidance and are not subject to test.
Parameter A Grades Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 5 µs typ To 0.01% of Full-Scale Range. V
REF
= 0 V
DAC Latch Alternately Loaded with All 0s and All 1s
Digital to Analog Glitch Impulse 60 nV-s typ V
REF
= 1.23 V. DAC Register Alternately Loaded
with All 0s and All 1s
Multiplying Feedthrough Error –75 dB max DAC Latch Loaded with All 0s
Output Capacitance 60 pF max All 1s Loaded to DAC
30 pF max All 0s Loaded to DAC
Digital Feedthrough 5 nV-s typ Feedthrough to the DAC Output with LD1, LD2
High and Alternate Loading of All 0s and All 1s
into the Input Shift Register
Digital Feedthrough (AD7945, AD7948) 5 nV-s typ Feedthrough to the DAC Output with CS High
and Alternate Loading of All 0s and All 1s to the
DAC Bus
Total Harmonic Distortion –83 dB typ
Output Noise Spectral Density
@ 1 kHz 25 nV/√Hz typ All 1s Loaded to DAC. V
REF
= 1.23 V
Specifications subject to change without notice.
AD7943/AD7945/AD7948
REV. B –5–
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
STB
2
60 40 ns min STB Pulsewidth
t
DS
15 10 ns min Data Setup Time
t
DH
35 25 ns min Data Hold Time
t
SRI
55 35 ns min SRI Data Pulsewidth
t
LD
55 35 ns min Load Pulsewidth
t
CLR
55 35 ns min CLR Pulsewidth
t
ASB
0 0 ns min Min Time Between Strobing Input Shift
Register and Loading DAC Register
t
SV
3
60 35 ns max STB Clocking Edge to SRO Data Valid Delay
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input.
2
STB mark/space ratio range is 60/40 to 40/60.
3
t
SV
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
t
STB
STB1,
STB2,
STB4
STB3
t
DS
t
DH
t
SRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
DB0(N–1)
DB10(N–1)
LD1,
LD2,
CLR
SRO
t
SV
t
LD
, t
CLR
t
ASB
Figure 1. AD7943 Timing Diagram
TO OUTPUT
PIN
C
L
50pF
1.6mA
I
OL
+2.1V
I
OH
200mA
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS
1
AD7943/AD7945/AD7948
REV. B–6–
AD7945 TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
DS
35 20 ns min Data Setup Time
t
DH
10 10 ns min Data Hold Time
t
CS
60 40 ns min Chip Select Setup Time
t
CH
0 0 ns min Chip Select Hold Time
t
WR
60 40 ns min Write Pulsewidth
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA VALID
CS
t
CH
t
DS
t
DH
WR
DB11–DB0
t
CS
t
WR
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Limit @ Limit @
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.5 V to +5.5 V Units Description
t
DS
45 30 ns min Data Setup Time
t
DH
10 10 ns min Data Hold Time
t
CWS
0 0 ns min CSMSB or CSLSB to WR Setup Time
t
CWH
0 0 ns min CSMSB or CSLSB to WR Hold Time
t
LWS
0 0 ns min LDAC to WR Setup Time
t
LWH
0 0 ns min LDAC to WR Hold Time
t
WR
60 40 ns min Write Pulsewidth
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DATA
VALID
DATA
VALID
WR
t
CWS
t
CWH
t
CWS
t
CWH
t
LWH
t
LWS
t
DH
t
DS
t
WR
t
WR
t
DH
t
DS
CSMSB
CSLSB
LDAC
DB7–DB0
Figure 4. AD7948 Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AD7945BR

Mfr. #:
Buy AD7945BR
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 3.3V/5V Multiplying 12-Bit Parallel IF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet