14©2016 Integrated Device Technology, Inc. Revision C, February 26, 2016
813N322I-02 Datasheet
Schematic Layout
Figure 4 (next page) shows an example of 813N322I-02 application
schematic. In this example, the device is operated at V
CC
= V
CCA
=
V
CCX
= V
CCO
= 3.3V. The inputs are driven by a 3.3V LVPECL driver
and an LVDS driver. Two examples of LVPECL output terminations
are shown in this schematic.
A three pole loop filter is used for the greater reduction of 8kHz or
10kHz phase detector spurs relative to that afforded by a two pole
loop filter. It is recommended that the loop filter components be laid
out on the 813N322I-02 side of the PCB directly adjacent to the LF0
and LF1 pins.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 813N322I-02 provides
separate V
CC
, V
CCA
, V
CCX
and V
CCO
power supplies for each jitter
attenuator to isolate any high switching noise from coupling into the
internal PLLs.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to the
power pins as possible. This is represented by the placement of
these capacitors in the schematic. If space is limited, the ferrite
beads, 10µF and 0.1µF capacitor connected to 3.3V can be placed
on the opposite side of the PCB. If space permits, place all filter
components on the device side of the board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
