8©2016 Integrated Device Technology, Inc. Revision C, February 26, 2016
813N322I-02 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: PSNR results achieved by injecting noise on V
CCA
supply pin with no external filter network.
NOTE 5: Lock Time measured from power-up to stable output frequency.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
IN
Input Frequency 0.008 156.25 MHz
f
OUT
Output Frequency 19.44 622.08 MHz
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
77.76MHz f
OUT
, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.823 0.951 ps
155.52MHz f
OUT
, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.674 0.788 ps
622.08MHz f
OUT
, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.616 0.736 ps
tsk(o) Output Skew; NOTE 2, 3 50 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 450 ps
odc Output Duty Cycle 48 52 %
PSNR
Power Supply Noise
Rejection; NOTE 4
VPP = 50mV Sine Wave,
Integration Range: 10kHz - 10MHz
-95 dB
t
LOCK
Output-to-Input Phase
Lock Time; NOTE 5
Reference Clock Input is ±50ppm from
Nominal Frequency
3s
