813N322CKI-02LFT Datasheet 813N322CKI-02LFT | P16-P18

813N322I-02 Datasheet

Jitter Attenuator External Components

Choosing the correct external components and having a proper

printed circuit board (PCB) layout is a key task for quality operation of

the Jitter Attenuator. In choosing a crystal, special precaution must

be taken with load capacitance (C

), frequency accuracy and

temperature range.

The crystal’s C

characteristic determines its resonating frequency

and is closely related to the center tuning of the crystal. The total

external capacitance seen by the crystal when installed on a PCB is

the sum of the stray board capacitance, IC package lead

capacitance, internal device capacitance and any installed tuning

capacitors (C

TUNE

). The recommended C

in the Crystal Parameter

Table balances the tuning range by centering the tuning curve for a

typical PCB. If the crystal C

is greater than the total external

capacitance, the crystal will oscillate at a higher frequency than the

specification. If the crystal C

is lower than the total external

capacitance, the crystal will oscillate at a lower frequency than the

specification. Tuning adjustments might be required depending on

the PCB parasitics or if using a crystal with a higher C

specification.

In addition, the frequency accuracy specification in the crystal

characteristics table are used to calculate the APR (Absolute Pull

Range).

Crystal Characteristics

The VCXO-PLL Loop Bandwidth Selection Table shows R

, C

and R

SET

values for recommended high, mid and low loop bandwidth

configurations. The device has been characterized using these

parameters. In addition, the digital VCXO gain (K

VCXO

) has been

provided for additional loop filter requirements.

Jitter Attenuator Characteristics Table

Jitter Attenuator Loop Bandwidth Selection Table (2

Order Loop Filter)

NOTE: See Application schematic to identify loop filter components R

R3, C3 and R

SET.

LF0

LF1

ISET

XTAL_IN

XTAL_OUT

SET

TUNE

3.3pF

TUNE

3.3pF

27MHz

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 27 MHz

Frequency Tolerance ±20 ppm

Frequency Stability ±20 ppm

Operating Temperature Range -40 +85

Load Capacitance 10 pF

Shunt Capacitance 4pF

ESR Equivalent Series Resistance 40



Aging @ 25

C First Year ±3 ppm

Symbol Parameter Typical Units

VCXO

VCXO Gain 2.018 kHz/V

Bandwidth Crystal Frequency R

(k)C

(µF) C

(µF) R3 (k)C3 (k)R

SET

(k)

9Hz (Low) 27MHz 140 10 0.01 0 Do not Populate 2.21

44Hz (Mid) 27MHz 487 1 0.0022 0 Do not Populate 1.87

56Hz (High) 27MHz 487 1 0.0022 0 Do not Populate 1.5

813N322I-02 Datasheet

For applications in which there is substantial low frequency jitter in

the input reference and the phase detector frequency of 8kHz or

10kHz lies in or near a jitter mask, a three pole filter is recommended.

Suggested part values are in the table below. Note that the option of

a three pole filter can be left open by laying out the three pole filter

but setting R3 to 0 ohms and not populating C3. Refer to the

application schematic for a specific example.

Jitter Attenuator Loop Bandwidth Selection Table (3

Order Loop Filter)

NOTE: See Application schematic to identify loop filter components R

R3, C3 and R

SET.

The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept

short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal

components.

Bandwidth Crystal Frequency R

(k)C

(µF) C

(µF) R3 (k)C3 (k)R

SET

(k)

14Hz (Low) 27MHz 300 1 0.01 220 0.001 3.0

29Hz (Mid) 27MHz 470 1 0.0022 220 0.001 2.21

52Hz (High) 27MHz 520 1 0.0022 220 0.001 1.5

813N322I-02 Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 5. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

SOLDERSOLDER

PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

813N322CKI-02LFT

Mfr. #:

Buy 813N322CKI-02LFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner Jitter Atten 4th Gen 2-Input 27MHz 10pF

Lifecycle:

New from this manufacturer.

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