AMIS49587C5871RG Datasheet AMIS49587C5871G, AMIS49587C5871RG, AMIS49587C5872RG | P16-P18

AMIS−49587

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5 INTRODUCTION

5.1 GENERAL DESCRIPTION

The AMIS−49587 is a single chip half duplex S−FSK

modem dedicated to power line carrier (PLC) data

transmission on low− or medium−voltage power lines. The

device offers complete handling of the protocol layers from

the physical up to the MAC. AMIS−49587 complies with the

CENELEC EN 50065−1 and the IEC 61334−5−1 standards.

It operates from a single 3.3 V power supply and is

interfaced to the power line by an external power driver and

transformer. An internal PLL is locked to the mains

frequency and is used to synchronize the data transmission

at data rates of 300, 600, 1200 and 2400 baud for a 50Hz

mains frequency, or 360, 720, 1440 and 2880 baud for a

60 Hz mains frequency. In both cases this corresponds to

3,6,12 or 24 data bits per half cycle of the mains period.

S−FSK is a modulation and demodulation technique that

combines some of the advantages of a classical spread

spectrum system (e.g. immunity against narrow band

interferers) with the advantages of the classical FSK system

(low complexity). The transmitter assigns the space

frequency f

S to “data 0” and the mark frequency fM to “data

1”. The difference between S−FSK and the classical FSK

lies in the fact that f

S and fM are now placed far from each

other, making their transmission quality independent from

each other (the strengths of the small interferences and the

signal attenuation are both independent at the two

frequencies). The frequency pairs supported by the

AMIS−49587 are in the range of 9−95 kHz with a typical

separation of 10 kHz.

The conditioning and conversion of the signal is

performed at the analog front−end of the circuit. The further

processing of the signal and the handling of the protocol is

digital. At the back−end side, the interface to the application

is done through a serial interface. The digital processing of

the signal is partitioned between hardwired blocks and a

microprocessor block. The microprocessor is controlled by

firmware. Where timing is most critical, the functions are

implemented with dedicated hardware. For the functions

where the timing is less critical, typically the higher level

functions, the circuit makes use of the ARM 7TDMI

microprocessor core.

The processor runs DSP algorithms and, at the same time,

handles the communication protocol. The communication

protocol, in this application, contains the MAC = Medium

Access Control Layer. The program running on the

microprocessor is stored into ROM. The working data

necessary for the processing is stored in an internal RAM. At

the back−end side the link to the application hardware is

provided by a Serial Communication Interface (SCI). The

SCI is an easy to use serial interface, which allows

communication between an external processor used for the

application software and the AMIS−49587 modem. The SCI

works on two wires: TXD and RXD. Baud rate is

programmed by setting 2 bits (BR0, BR1).

Because the low protocol layers are handled in the circuit,

the AMIS−49587 provides an innovative architectural split.

Thanks to this, the user has the benefit of a higher level

interface of the link to the PLC medium. Compared to an

interface at the physical level, the AMIS−49587 allows

faster development of applications. The user just needs to

send the raw data to the AMIS−49587 and no longer has to

take care of the protocol detail of the transmission over the

specific medium. This last part represents usually 50 percent

of the software development costs.

Minor User TypeMajor User Type

SPY

Application

AMIS−49587in

MONITOR mode

TEST

Application

AMIS−49587in

TEST mode

CLIENT

Application

AMIS−49587in

MASTER mode

SERVER

Application

AMIS−49587in

SLAVE mode

SERVER

Application

AMIS−49587 in

SLAVE mode

Figure 8. Application Examples

AMIS−49587 intended to connect equipment using

Distribution Line Carrier (DLC) communication. It serves

two major and two minor types of applications:

• Major types:

♦ Master or Client:

A Master is a client to the data served by one or

many slaves on the power line. It collects data from

and controls the slave devices. A typical application

is a concentrator system.

♦ Slave or Server:

A Slave is a server of the data to the Master. A

typical application is an electricity meter equipped

with a PLC modem.

• Minor type:

♦ Spy or Monitor:

Spy or Monitor mode is used to only listen to the

data that comes across the power line. Only the

physical layer frame correctness is checked. When

AMIS−49587

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the frame is correct, it is passed to the external

processor.

♦ Test Mode:

The Test Mode is used to test the compliance of a

PLC modem conforms to CENELEC. EN 50065−1

by a Continuous broadcast of f

or f

5.1.1. CONVERTING AMIS−49587−BASED DESIGNS

TO NCN49597

The NCN49597 is designed to allow easy adaptation of

printed circuit board designs using the AMIS−49587. All

connected pins of the latter (QFN package) are present in the

same location in the NCN49597.

Four important hardware changes must be noted.

Most of the not−connected (NC) pins of the AMIS−49587

are functional in the NCN49597. If these pins were

previously connected to ground (a commendable practice)

this must be taken into account. IO4–IO10 are usually

configured as inputs and can therefore be grounded safely.

However, it must be considered that some NC pins of

AMIS−49587 are outputs in the NCN49597. These include

SDO, SCK and, CSB. IO0 and IO1 are used typically used

by the firmware as status indicators. IO3 is used by the ON

PL110 firmware for controlling the amplifier enable signal.

Secondly, the NCN49597 incorporates an internal 1.8 V

regulator to power the digital core. For stability, a 1 mF

capacitor to ground must be connected on pin 19

(VDD1V8).

In addition, the lowest baud rate setting of the

AMIS−49587 serial interface (BR0 & BR1 pulled low; 4800

baud) has been replaced by 115200 baud. All other BR0 and

BR1 settings will result in the same baud rate.

Finally, a 48 MHz crystal is required for the NCN49597;

the AMIS−49587 used a 24 MHz crystal.

The firmware running on the modem has been updated

substantially compared to the AMIS−49587. As a result, the

interface protocol between the user microcontroller and the

modem is completely different. Refer to the firmware

datasheet for details.

5.2 FUNCTIONAL DESCRIPTION

The block diagram below represents the main functional

units of the AMIS−49587:

Figure 9. S−FSK Modem AMIS−49587 Block Diagram

Communication Controller

ARM

Risc

Core

Serial

Comm.

Interface

Local Port

Test

Control

POR

Watchdog

Timer 1 & 2

Interrupt

Control

Data

RAM

Program

ROM

AAF AGC A/D

REF

S−FSK

Demodulator

Receiver (S−FSK Demodulator)

Clock and Control

Zero

crossing

PLL OSC

Clock Generator

& Timer

Transmit Data

& Sine Synthesizer

D/A

Filter

Transmitter (S−FSK Modulator)

RX_DATA

RESB

JTAG I /F

TEST

TX_ENB

TX_OUT

ALC_IN

RX_OUT

RX_IN

REF_OUT

M50Hz_IN

XIN XOUTVDDA VSSA VDDD VSSD

AMIS−49587

PC20091019.2

TO Power Amplifier

FROM Line Coupler

TO Applicatio

Micro Contro

ller

TxD

RxD

T_REQ

BR0

BR1

CRC

TX_DATA / PRE_SLOT

5.2.1 Transmitter

The AMIS−49587 Transmitter function block prepares

the communication signal which will be sent on the

transmitting channel during the transmitting phase. This

block is connected to a power amplifier which injects the

output signal on the mains through a line−coupler.

5.2.2 Receiver

The analog signal coming from the line−coupler is low

pass filtered in order to avoid aliasing during the conversion.

Then the level of the signal is automatically adapted by an

automatic gain control (AGC) block. This operation

maximizes the dynamic range of the incoming signal. The

signal is then converted to its digital representation using

sigma delta modulation. From then on, the processing of the

data is done in a digital way. By using dedicated hardware,

a direct quadrature demodulation is performed. The signal

demodulated in the base band is then low pass filtered to

reduce the noise and reject the image spectrum.

Clock and Control

According to the IEC−61334−5−1 standard, the frame

data is transmitted at the zero crossing of the mains voltage.

In order to recover the information at the zero crossing, a

zero crossing detection of the mains is performed. A

phase−locked loop (PLL) structure is used in order to allow

AMIS−49587

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a more reliable reconstruction of the synchronization. This

PLL permits as well a safer implementation of the

”repetition with credit” function (also known as chorus

transmission). The clock generator makes use of a precise

quartz oscillator master. The clock signals are then obtained

by the use of a programmed division scheme. The support

circuits are also contained in this block. The support circuits

include the necessary blocks to supply the references

voltages for the AD and DA converters, the biasing currents

and power supply sense cells to generate the right power off

and startup conditions.

20 ms

24 bit @ 1200 baud

Figure 10. Data Stream is in Sync with Zero

Crossings of the Mains (Example for 50 Hz)

5.2.3 Communication Controller

The Communication Controller block includes the

micro−processor, its peripherals: RAM, ROM, UART,

TIMER, and the Power on reset. The processor uses the

ARM Reduced Instruction Set Computer (RISC)

architecture optimized for IO handling. For most of the

instructions, the machine is able to perform one instruction

per clock cycle. The microcontroller contains the necessary

hardware to implement interrupt mechanisms, timers and is

able to perform byte multiplication over one instruction

cycle. The microcontroller is programmed to handle the

physical layer (chip synchronization), and the MAC layer

conform to IEC 61334−5−1. The program is stored in a

masked ROM. The RAM contains the necessary space to

store the working data. The back−end interface is done

through the Serial Communication Interface block. This

back−end is used for data transmission with the application

micro controller (containing the application layer for

concentrator, power meter, or other functions) and for the

definition of the modem configuration.

5.2.4 Local Port

The controller uses 3 output ports to inform about the

actual status of the PLC communication. RX_DATA

indicates if Receiving is in progress, or if AMIS−49587 is

waiting for synchronization, or of it configures. CRC

indicates if the received frames are valid (CRC = OK).

TX_DATA / PRE_SLOT is the output for either the

transmitting data (TX_DATA) or a synchronization signal

with the time−slots (PRE_SLOT).

5.2.5 Serial Communication Interface

The local communication is a half duplex asynchronous

serial link using a receiving input (RxD) and a transmitting

output (TxD). The input port T_REQ is used to manage the

local communication with the application micro controller

and the baud rate can be selected depending on the status of

two inputs BR0, BR1. These two inputs are taken in account

after an AMIS−49587 reset. Thus when the application

micro controller wants to change the baud rate, it has to set

the two inputs and then provoke a reset.

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AMIS49587C5871RG

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Manufacturer:

ON Semiconductor

Description:

Network Controller & Processor ICs C587- NAF- AMIS49587

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AMIS49587C5871RG

AMIS49587C5871RG

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