AMIS49587C5871RG Datasheet AMIS49587C5871G, AMIS49587C5871RG, AMIS49587C5872RG | P22-P24

AMIS−49587

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6.1.4 Clock Generator and Timer

The CHIP_CLK and f

CLK

are used to generate a number

of timing signals used for the synchronization and interrupt

generation. The timing generation has a fixed repetition rate

which corresponds to the length of a physical subframe. (see

paragraph Send and Receive network data).

The timing generator is the same for transmit and receive

mode. When AMIS−49587 switches from receive to

transmit and back from transmit to receive, the

R_CHIP_CNT counter value is maintained. As a result all

timing signals for receive and transmit have the same

relative timing. The following timing signals are defined as:

BIT_CLK

63 64 6528712872 102879 2 3 4 5 6 7 8 9

CHIP_CLK

BYTE_CLK

FRAME_CLK

PRE_FRAME_CLK

PRE_BYTE_CLK

R_CHIP_CNT

PRE_SLOT

Start of the physical subframe

Figure 16. Timing Signals

CHIP_CLK is the output of the PLL and 8 times the bit rate on the physical interface. See also paragraph 50/60 Hz PLL

BIT_CLK is active at counter values 0,8,16, .. 2872 and inactive at all other counter values. This signal is used to indicate the

transmission of a new bit.

BYTE_CLK is active at counter values 0,64,128, .. 2816 and inactive at all other counter values. This signal is used to indicate

the transmission of a new byte.

FRAME_CLK is active at counter values 0 and inactive at all other counter values. This signal is used to indicate the

transmission or reception of a new frame.

PRE_BYTE_CLK is a signal which is 8 CHIP_CLK sooner than BYTE_CLK. This signal is used as an interrupt for the

internal microcontroller and indicates that a new byte for transmission must be generated.

PRE_FRAME_CLK is a signal which is 8 CHIP_CLK sooner than FRAME_CLK. This signal is used as an interrupt for the

internal microcontroller and indicates that a new frame will start at the next FRAME_CLK.

PRE_SLOT is logic 1 between the rising edge of PRE_FRAME_CLK and the rising edge of FRAME_CLK. This signal can

be provided at the digital output pin TX_DATA_PRE_SLOT when R_CONF[7] = 0 (See paragraph WriteConfigRequest, field

TX_DATA_PRE−SLOT_SEL) and can be used by the external host controller to synchronize its software with the

FRAME_CLK of AMIS−49587.

AMIS−49587

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6.2 TRANSMITTER PATH DESCRIPTION (S−FSK

MODULATOR)

For the generation of the space and mark frequencies, the

direct digital synthesis (DDS) of the sine wave signals is

performed under the control of the microprocessor. After a

signal conditioning step, a digital to analog conversion is

performed. As for the receive path, a sigma delta modulation

technique is used. In the analog domain, the signal is low

pass filtered, in order to remove the high frequency

quantization noise, and passed to the automatic level

controller (ACL) block, where the level of the transmitted

signal can be adjusted. The determination of the signal level

is done through the sense circuitry.

Figure 17. Transmitter Block Diagram

Transmitter (S−FSK Modulator)

ARM

Interface

Control

TX_OUT

Transmit Data

& Sine Synthesizer

D/A

Filter

ALC

control

ALC_IN

TO RECEIVER

TX_EN

6.2.1 ARM Interface and Control

The interface with the ARM consists in a 8−bit data

registers R_TX_DATA, 2 control registers R_TX_CTRL

and R_ALC_CTRL, a flag TX_RXB defining transmit and

receive and 2 16−bit wide frequency step registers R_FM

and R_FS defining f

(mark frequency = data 1) and f

(space frequency = data 0). All these registers are memory

mapped. Some of them are for internal use only and cannot

be accessed by the user.

The processing of the physical frame (preamble, MAC

address, CRC) is done by the ARM.

6.2.2 Sine Wave Generator

A sine wave is generated with a direct digital synthesizer

DDS. The synthesizer generates in transmission mode a sine

wave either for the space frequency (f

, data 0) or for the

mark frequency (f

, data1). In reception the synthesizer

generates the sine and cosine waves for the mixing process,

, f

(space and mark signals in phase and

quadrature). The space and mark frequencies are defined in

an individual step 16 bit wide register.

Table 24. FS AND FM STEP REGISTERS

ARM

Hard

Reset

Soft

Reset

Description

R_FS[15:0] 0000h 0000h Step register for the

space frequency f

R_FM[15:0] 0000h 0000h Step register for the

mark frequency f

The space and mark frequency can be calculated as:

• f

= R_FS[15:0]_dec x f

DDS

• f

= R_FM[15:0]_dec x f

DDS

Or the content of both R_FS[15:0] and R_FM[15:0] are

defined as:

• R_FS[15:0]_dec = Round(2

x f

DDS

)

• R_FM[15:0]_dec = Round(2

x f

DDS

)

Where f

DDS

= 3 MHz is the direct digital synthesizer

clock frequency.

After a hard or soft reset or at the start of the transmission

(when TX_RXB goes from 0 to 1) the phase accumulator

AMIS−49587

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must start at it’s 0 phase position, corresponding with a 0 V

output level. When switching between f

and f

the phase

accumulator must give a continuous phase and not restart

from phase 0.

When AMIS−49587 goes into receive mode (when

TX_RXB goes from 1 to 0) the sine wave generator must

make sure to complete the active sine period.

The control logic for the transmitter generates a signal

TX_ENB to enable the external power amplifier. TX_ENB

is 1 when the AMIS−49587 is in receive mode. TX_ENB is

0 when AMIS−49587 is in transmit mode. When going from

transmit to receive mode (TX_RXB goes from 1 to 0) the

TX_ENB signal is kept active for a short period of t

dTX_ENB

The control logic for the transmitter generates a signal

TX_DATA which corresponds to the transmitted S−FSK

signal. When transmitting f

TX_DATA is logic 1. When

transmitting f

TX_DATA is logic 0. When the transmitter

is not enabled (TX_RXB = 0) TX_DATA goes to logic 1 at

the next BIT_CLK.

Figure 18. TX_ENB Timing

TX_OUT

TX_ENB

TX_RXB

TX_DATA

BIT_CLK

dTX_ENB

6.2.3 DA Converter

A digital to analog SD converter converts the sine wave

digital word to a pulse density modulated (PDM) signal. The

PDM signal is converted to an analog signal with a first order

switched capacitor filter.

6.2.4 Low Pass Filter

A 3

order continuous time low pass filter in the transmit

path filters the quantization noise and noise generated by the

SD DA converter. The low pass filter has a circuit which

tunes the RC time constants of the filter towards the process

characteristics. The C values for the LPF filter are controlled

by the ARM micro controller.

6.2.5 Amplifier with Automatic Level Control (ALC)

The pin ALC_IN is used for level control of the

transmitter output level. First a peak detection is done. The

peak value is compared to 2 thresholds levels: VTL

ALC_IN

and VTH

ALC_IN

. The result of the peak detection is used to

control the setting of the level of TX_OUT. The level of

TX_OUT can be attenuated in 8 steps of 3 dB typical.

After hard or soft reset the level is set at minimum level

(maximum attenuation) When going to reception mode

(when TX_RXB goes from 1 to 0) the level is kept in

memory so that the next transmit frame starts with the old

level. The evaluation of the level is done during 1

CHIP_CLK period.

Depending on the value of peak level on ALC_IN the

attenuation is updated:

−Vp

ALC_IN

< VTL

ALC

: Increase the level with 1 step

− VTL

ALC

≤ Vp

ALC_IN

≤ VTH

ALC

: Don’t change the

level

−Vp

ALC_IN

> VTH

ALC

: Decrease the level with 1 step

The gain changes in the next CHIP_CLK period.

An evaluation phase and a level adjustment takes 2

CHIP_CLK periods. ALC operation is enabled only during

the first 16 CHIP_CLK cycles after a hard or soft reset or

after going into transmit mode.

The automatic level control can be disabled by setting

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AMIS49587C5871RG

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Network Controller & Processor ICs C587- NAF- AMIS49587

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