AMIS−49587
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11: 48 data bits per mains period = 2400 baud @ 50 Hz
MAINS_FREQ: 0: 50 Hz
1: 60 Hz
R_FS and R_FM step registers are defining the space and mark frequency. Explanation on the values can be found in paragraph
Sine wave generator. This register can be accessed via a WriteConfig_Request.
Table 31. FS AND FM STEP REGISTERS (See Table 41: Configuration Parameters)
ARM Register
Hard Reset Soft Reset Description
R_FS[15:0] 0000h 0000h Step register for the space frequency f
S
R_FM[15:0] 0000h 0000h Step register for the mark frequency f
M
R_ZC_ADJUST register defines the value which is pre−loaded in the PLL counter. This is used to fine tune the phase
difference between HIP_CLK, CIP_CLK and the – to + zero crossing of the mains. Explanation on the values can be found
in paragraph 50/60 Hz PLL. This register can be accessed via a WriteConfig_Request.
Table 32. ZC_ADJUST REGISTERS (See Table 41: Configuration Parameters)
ARM Register
Hard Reset Soft Reset Description
R_ZC_ADJUST[7:0] 02h 02h Fine tuning of phase difference between CHIP_CLK and rising
edge of Mains zero crossing
R_ALC_CTRL register enables or disables the Automatic Level Control. In case ALC is disabled the attenuation of the TX
output driver is fixed according to the value in R_ALC_CTRL[2:0]. Explanation on the attenuation values can be found in
paragraph Amplifier with Automatic Level Control. This register can be accessed via a WriteConfig_Request.
Table 33. ALC_CTRL REGISTERS (See appendix C)
ARM Register
Hard Reset Soft Reset Description
R_ALC_CTRL[3:0] 00h 00h Control register for the automatic level control
Where:
R_ALC_CTRL[3]: 0: Automatic level control is enabled
1: Automatic level control is disabled and attenuation is fixed
R_ALC_CTRL[2:0]: Fixed attenuation value
Table 34. FIXED TRANSMITTER OUTPUT
ATTENUATION
ALC_CTRL[2:0] Attenuation
000 0 dB
001 −3 dB
010 −6 dB
011 −9 dB
100 −12 dB
101 −15 dB
110 −18 dB
111 −21 dB
6.4.10 Reset and Low Power
AMIS−49587 has 2 reset mode: hard reset and soft reset.
The hard reset initializes the complete IC (hardware and
ARM) excluding the data RAM for the ARM. This makes
sure that start−up of hardware and ARM is guaranteed. A
hard reset is active when pin RESB = 0 or when the power
supply V
DD
< V
POR
(See Table 14 Power On Reset). When
switching on the power supply the output of the crystal
oscillator is disable until a few 1000 clock pulses have been
detected, this to enable the oscillator to start up.
The soft reset initializes part of the hardware. The soft
reset is activated when going into initialization mode for the
duration of maximum 1 CHIP_CLK. Initialization mode is
entered by R_CONF[5:3] = 000.
The concept of AMIS−49587 has a number of provisions
to have low power consumption. When working in transmit
mode the analogue receiver path and most of the digital
receive parts are disabled. When working in receive mode
the analog transmitter and most of the digital transmit parts,
except for the sine generation, are disabled.
When the pin RESB = 0 the power consumption is
minimal. Only a limited power is necessary to maintain the
bias of a minimum number of analog functions and the
oscillator cell.
