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840S07BYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
1©2016 Integrated Device Technology, Inc Revision A April 14, 2016
General Description
The 840S07I is a seven output LVCMOS/LVTTL Frequency
Synthesizer accepting crystal or single-ended reference clock
inputs. The 840S07I uses a 25MHz parallel resonant crystal to
generate 33.33MHz – 166.67MHz clock signals, replacing solutions
requiring multiple oscillator and fanout buffer solutions. The device
supports output slew rate control with two slew select pins
(SLEW[1:0]). The VCO operates at a frequency of 2GHz. The device
has 3 output banks, output QAA with one 33.33MHz – 166.67MHz
LVCMOS/LVTTL output, output QAB with one 125MHz
LVCMOS/LVTTL output and Bank B with three 33.33MHz –
166.67MHz LVCMOS/LVTTL outputs.
Output QAA and Bank B have their own dedicated frequency select
pins and can be independently set for the frequencies mentioned
above. Designed for networking and industrial applications, the
840S07I can also drive the high-speed clock inputs of
communication processors, DSPs, switches and bridges.
Features
• Five single-ended LVCMOS/LVTTL outputs
• Two REF_OUT LVCMOS/LVTTL clock outputs
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference input
• Supports the following output frequencies:
Output QAA/Bank B: 33.33MHz, 50MHz, 66.67MHz, 83.33MHz,
100MHz, 125MHz, 133.33MHz and 166.67MHz
Output QAB: 125MHz
• VCO frequency: 2GHz
• Slew rate control
• Voltage supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
840S07I
32-Lead TQFP, E-Pad
7mm x 7mm x1mm package body
Y Package
Top View
Pin Assignment
Block Diagram
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDA
VDD
XTAL_OUT
XTAL_IN
GND
REF_SEL
REF_IN
F_SELB2
GND
QAA
V
DDO_AA
GND
QB0
QB1
QB2
VDDO_B
nOE_REF
V
DDO_REF
REF_OUT0
REF_OUT1
GND
F_SELB1
MR/nOE
F_SELB0
SLEW1
SLEW0
F_SELAA1
F_SELAA0
GND
QAB
V
DDO_AB
F_SELAA2
0
1
PLL
VCO
2GHz
M = ÷80
÷NAA
NAB
÷16
÷NB
OSC
3
2
3
QAA
QAB
QB0
QB1
QB2
REF_OUT0
REF_OUT1
SLEW[1:0]
REF_IN
REF_SEL
XTAL_IN
XTAL_OUT
25MHz
25MHz
Pulldown
MR/nOE
Pulldown
Pulldown
Pulldown
Pulldown
[2, 1] Pulldown, [0] Pullup
nOE_REF
F_SELB[2:0]
F_SELAA[2:0]
Pullup
125MHz
840S07I
Data Sheet
Crystal-to-LVCMOS/LVTTL Frequency
Synthesizer
2©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1V
DDA
Power Analog supply pin.
2V
DD
Power Core supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
5, 13,
21, 24, 27
GND Power Power supply ground.
6 REF_SEL Input Pulldown
Reference select pin. When HIGH selects REF_IN. When LOW, selects
crystal. See Table 3D. LVCMOS/LVTTL interface levels.
7 REF_IN Input Pulldown
Single-ended reference clock input. Table 3B.
LVCMOS/LVTTL interface levels.
8,
14,
16
F_SELB2,
F_SELB1,
F_SELB0
Input Pulldown
Frequency select pins for Bank B outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
9 nOE_REF Input Pullup
Active low REF_OUT enable/disable pin. See Table 3F.
LVCMOS/LVTTL interface levels.
10 V
DDO_REF
Power Output supply pin for REF_OUTx clock outputs.
11,
12
REF_OUT0,
REF_OUT1
Output Single-ended reference clock outputs. LVCMOS/LVTTL interface levels.
15 MR/nOE Input Pulldown
Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (HI-Z).
When logic LOW, the internal dividers and the outputs are enabled.
See Table 3E. LVCMOS/LVTTL interface levels.
17 V
DDO_B
Power Output supply pin for QBx outputs.
18, 19, 20 QB2, QB1, QB0 Output Single-ended Bank QBx clock outputs. LVCMOS/ LVTTL interface levels.
22 V
DDO_AA
Power Output supply pin for QAA output.
23 QAA Output Single-ended QAA clock output. LVCMOS/LVTTL interface levels.
25 V
DDO_AB
Power Output supply pin for QAB output.
26 QAB Output Single-ended QAB clock output. LVCMOS/LVTTL interface levels.
28 F_SELAA0 Input Pullup
Frequency select pin for QAA output. See Table 3A.
LVCMOS/LVTTL interface levels.
29,
32
F_SELAA1,
F_SELAA2
Input Pulldown
Frequency select pins for QAA output. See Table 3A.
LVCMOS/LVTTL interface levels.
30, 31 SLEW0, SLEW1 Input Pulldown
Slew rate select pins for LVCMOS/LVTTL clock output.
LVCMOS/LVTTL interface levels.
3©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
Table 2. Pin Characteristics
Function Tables
Table 3A. Output QAA Frequency Select Function Table
NOTE: Using 25MHz reference.
Table 3B. Output QAB Frequency Select Function Table
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input
Capacitance
2pF
C
PD
Power
Dissipation
Capacitance
SLEW[1:0] = 00
V
DD
, V
DDO_REF,
V
DDO_AA,
V
DDO_AB,
V
DDO_B
= 3.465V
4pF
SLEW[1:0] = 11
V
DD
, V
DDO_REF,
V
DDO_AA,
V
DDO_AB,
V
DDO_B
= 3.465V
10 pF
SLEW[1:0] = 00, V
DD
= 3.465V,
V
DDO_REF,
V
DDO_AA,
V
DDO_AB,
V
DDO_B
=
2.625V
2.65 pF
SLEW[1:0] = 11, V
DD
= 3.465V,
V
DDO_REF,
V
DDO_AA,
V
DDO_AB,
V
DDO_B
=
2.625V
3pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output
Impedance
QAA, QAB,
QBx
V
DDO_AA,
V
DDO_AB,
V
DDO_B
= 3.3V 26
V
DDO_AA,
V
DDO_AB,
V
DDO_B
= 2.5V 28
REF_OUTx
V
DDO_REF
= 3.3V 35
V
DDO_REF
= 2.5V 34
Inputs Output Frequencies
F_SELAA2 F_SELAA1 F_SELAA0 NAA Divider Value QAA (MHz)
L L L 60 33.33
L L H 40 50 (default)
L H L 30 66.67
L H H 24 83.33
H L L 20 100
H L H 16 125
H H L 15 133.33
H H H 12 166.67
Inputs Output Frequency
XTAL_IN, REF_IN (MHz) M Divider Value NAB Divider Value QAB (MHz)
25 80 16 125
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

840S07BYILF

Mfr. #:
Buy 840S07BYILF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner QUICClocks
Lifecycle:
New from this manufacturer.
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