11©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 840S07I provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD
, V
DDA
and V
DDO_X
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
DD
pin and also shows that V
DDA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 2. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
Figure 2. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
GROUND PLANE
LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER
PIN
PIN PAD
SOLDER
