7©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, V
DD
= V
DDO_REF
= V
DDO_AA
= V
DDO_AB
= V
DDO_B
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO_X
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: Jitter performance using XTAL inputs.
NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
QAB 125 MHz
QAA, QB[0:2] 33.33 166.67 MHz
tsk(o) Output Skew; NOTE 1, 2 f
OUT
= 125MHz; SLEW[1:0] = 00 485 ps
tsk(b)
Bank Skew;
NOTE 2, 3
QB[0:2] f
OUT
= 125MHz; SLEW[1:0] = 00 110 ps
tjit(per) Period Jitter, RMS; NOTE 4 f
OUT
= 125MHz; SLEW[1:0] = 00 7 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 f
OUT
= 125MHz; SLEW[1:0] = 00 90 ps
t
SLEW
Slew Rate,
Single-ended Output
Clock; NOTE 5
QAA
SLEW[1:0] = 00,
Rise/Fall Time: 20% to 80%
1.93 3.0 V/ns
QAB 2.84 4.75 V/ns
QB[0:2] 2.59 4.25 V/ns
QAA
SLEW[1:0] = 01,
Rise/Fall Time: 20% to 80%
1.76 2.75 V/ns
QAB 2.45 4.25 V/ns
QB[0:2] 2.23 3.75 V/ns
QAA
SLEW[1:0] = 10,
Rise/Fall Time: 20% to 80%
1.58 2.50 V/ns
QAB 1.88 3.0 V/ns
QB[0:2] 1.80 2.95 V/ns
QAA
SLEW[1:0] = 11,
Rise/Fall Time: 20% to 80%
0.98 1.65 V/ns
QAB 1.03 1.75 V/ns
QB[0:2] 1.01 1.75 V/ns
t
LOCK
PLL Lock Time SLEW[1:0] = 00 20 ms
odc Output Duty Cycle
f
OUT
125MHz; SLEW[1:0] = 00 47 53 %
f
OUT
> 125MHz; SLEW[1:0] = 00 45 55 %
