13©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
Schematic Example
Figure 5 shows an example of the 840S07I application schematic. In
this example, the device is operated at V
DD
= V
DDO_AA
= V
CCO_AB
=
V
CCO_B
= = V
CCO_REF
= 3.3V. The 18pF parallel resonant 25MHz
crystal is used. The C1 = 22pF and C2 = 22pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy. Two
examples of LVCMOS termination are shown in this schematic. The
decoupling capacitors should be located as close as possible to the
power pin.
Figure 5. 840S07I Schematic Layout
QB2
SLEW1
Zo = 50
VDD
C5
0.1u
Logic Control Input Examples
V DDO_REF=3.3V
VDDO_AB=3.3V
R5 27
MR_nOE
To Logic
Input
pins
F_SELB2
C9
0.1u
C4
10u
VDD
Set Logic
Input to
'1'
Note: This device requires a
reset signal at nMR after
power-up to function
properly.
nREF_OE
REF_SEL
REF_OUT1
RU2
Not Install
Set Logic
Input to
'0'
R4
43
Zo = 50 Ohm
C7
0.1u
C6
0.01u
F_SELAA2
R2 24
VDD
VDD
XTA L_O U T
C3
0.01u
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VDDA
VDD
XTA L_O U T
XTA L_I N
GND
REF_SEL
REF_IN
F_SELB2
nREF_OE
VDDO_REF
REF_OUT0
REF_OUT1
GND_REF
F_SELB1
MR/nOE
F_SELB0
VDDO_B
QB2
QB1
QB0
GND
VDDO_AA
QAA
GND
F_SELAA2
SLEW1
SLEW0
F_SELAA1
F_SELAA0
GND
QAB
VDDO_AB
C8
0.1u
To Logic
Input
pins
VDDA
VDDO_AA
R3 24
QAA
RU1
1K
LVCMOS
VDDO_AB
SLEW0
C1
22pF
F_SELAA0
QAB
Zo = 50
VDDO_AA=3.3V
XTAL_IN
RD2
1K
R1
10
V DDO_B=3.3V
VDDO_REF
F_SELB0
QB0
VDD=3.3V
Zo = 50C2
22pF
VDDO_B
VDD
LVCMOS
QB1
F_SELB1
REF_OUT0
LVCMOS
X1
25MHz, CL=18pF
RD1
Not Install
Ro ~ 7 Ohm
Q1
Driver_LVCMOS
F_SELAA1
VDD
VDD
REF_IN
14©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 840S07I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 840S07I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The
following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
The maximum current at 85°C is as follows:
I
DD_MAX
= 168.5mA
I
DDA_MAX
= 20.96mA
I
DDO_MAX
= 74.11mA
Core Output Power Dissipation
Power (core)
MAX
= V
DD_MAX
* (I
DD
+ I
DDA
) = 3.465V *(168.5mA + 20.96mA) = 656.51mW
Power (output)
MAX
= V
DDO_MAX
* I
DDO
= 3.465V *74.11mA = 256.80mW
LVCMOS Output Power Dissipation
Output Impedance R
OUT
Power Dissipation due to Loading 50 to V
DD
/2
Output Current I
OUT
= V
DD_MAX
/ [2 * (50 + R
OUT
)] = 3.465V / [2 * (50 + 35)] = 20.38mA
Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 35 * (20.38mA)
2
= 14.54mW per output
Total Power Dissipation on the R
OUT
Total Power (R
OUT
) = 14.54mW * 7 = 101.8mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = C
PD
* Frequency * (V
DDO
)
2
= 10pF * 25MHz * (3.465V)
2
= 3mW per output
Total Power (25MHz) = 3mW * 2 = 6mW
Dynamic Power Dissipation at 166.67MHz
Power (166.67MHz) = C
PD
* Frequency * (V
DDO
)
2
= 10pF * 166.67MHz * (3.465V)
2
= 20mW per output
Total Power (166.67MHz) = 20mW * 5 = 100.1mW
Total Power Dissipation
Total Power
= Power (core) + Power (output) + Total Power (25MHz + Total Power (166.67MHz)
= 656.51mW + 256.80mW + 101.8mW + 6.0mW + 100.1mW
= 1121.15mW
15©2016 Integrated Device Technology, Inc Revision A April 14, 2016
840S07I Data Sheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 30.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.121W *30.6°C/W = 119.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance
JA
for 32 Lead TQFP, E-Pad, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 36.2°C/W 30.6°C/W 29.2°C/W

840S07BYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner QUICClocks
Lifecycle:
New from this manufacturer.
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