Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. General description
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider
data/address paths of buses carrying parity.
The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and
master reset (pin nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
It is designed for V
CC
operation from 2.5 V to 3.0 V with I/O compatibility to 5 V.
2. Features
Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
5 V I/O compatible
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up 3-state
Power-up reset
No bus current loading when output is tied to 5 V bus
Output capability: +64 mA to 32 mA
Latch-up protection:
JESD78: exceeds 500 mA
ESD protection:
MIL STD 883, method 3015: exceeds 2000 V
Machine Model: exceeds 200 V
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable;
3-state
Rev. 04 — 2 August 2005 Product data sheet
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 2 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3. Quick reference data
4. Ordering information
Table 1: Quick reference data
T
amb
= 25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
t
PLH
propagation delay
nCP to nQx
C
L
= 50 pF; V
CC
= 2.5 V 1.5 2.9 4.5 ns
C
L
= 50 pF; V
CC
= 3.3 V 1.0 2.3 3.1 ns
t
PHL
propagation delay
nCP to nQx
C
L
= 50 pF; V
CC
= 2.5 V 1.4 2.7 4.2 ns
C
L
= 50 pF; V
CC
= 3.3 V 1.0 2.1 2.9 ns
C
i
input capacitance V
I
= 0 V or V
CC
-3-pF
C
o
output capacitance V
I/O
= 0 V or V
CC
-9-pF
I
CC
quiescent supply
current
outputs disabled;
V
CC
= 2.5 V
-40-µA
outputs disabled;
V
CC
= 3.3 V
-70-µA
Table 2: Ordering information
Type number Package
temperature range Name Description Version
74ALVT16823DL 40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads;
body width 7.5 mm
SOT371-1
74ALVT16823DGG 40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1

74ALVT16823DGGY

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops 18-Bit Bus-Interface D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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