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74ALVT16823DGGY

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 9 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
10. Static characteristics
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T
amb
=
−
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ Max Unit
V
CC
= 2.5 V ± 0.2 V
[1]
V
IK
input clamping voltage V
CC
= 2.3 V; I
IK
= −18 mA - −0.85 −1.2 V
V
OH
HIGH-level output voltage V
CC
= 2.3 V to 2.7 V; I
OH
= −100 µAV
CC
− 0.2 V
CC
-V
V
CC
= 2.3 V; I
OH
= −8 mA 1.8 2.5 - V
V
OL
LOW-level output voltage V
CC
= 2.3 V; I
OL
= 100 µA - 0.07 0.2 V
V
CC
= 2.3 V; I
OL
= 24 mA - 0.3 0.5 V
V
CC
= 2.3 V; I
OL
= 8 mA - - 0.4 V
V
OL(pu)
power-up LOW-level output
voltage
V
CC
= 2.7 V; I
O
= 1 mA;
V
I
=V
CC
or GND
[2]
- - 0.55 V
I
LI
input leakage current
control pins V
CC
= 2.7 V; V
I
= V
CC
or GND - 0.1 ±1 µA
V
CC
= 0 V to 2.7 V; V
I
= 5.5 V - 0.1 10 µA
I/O data pins V
CC
= 2.7 V; V
I
= V
CC
[3]
- 0.1 1 µA
V
CC
= 2.7 V; V
I
= 0 V
[3]
- +0.1 −5 µA
I
OFF
off current V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V - +0.1 ±100 µA
I
HOLD
bus hold current data inputs V
CC
= 2.3 V; V
I
= 0.7 V
[4]
- 100 - µA
V
CC
= 2.3 V; V
I
= 1.7 V
[4]
- −70 - µA
I
EX
external current into output output HIGH-state when V
O
>V
CC
;
V
O
= 5.5 V; V
CC
= 2.3 V
- 10 125 µA
I
PU
power-up 3-state output
current
V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
[5]
-1±100 µA
I
PD
power-down 3-state output
current
V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
[5]
-1±100 µA
I
OZ
3-state output current V
CC
= 2.7 V; V
I
= V
IL
or V
IH
output HIGH state; V
O
= 2.3 V - 0.5 5 µA
output LOW-state; V
O
= 0.5 V - +0.5 −5 µA
I
CC
quiescent supply current V
CC
= 2.7 V; V
I
= GND or V
CC
; I
O
= 0 A
outputs HIGH-state - 0.04 0.1 mA
outputs LOW-state - 2.7 4.5 mA
outputs disabled
[6]
- 0.04 0.1 mA
∆I
CC
additional quiescent supply
current per input pin
V
CC
= 2.3 V to 2.7 V; one input at
V
CC
− 0.6 V, other inputs at V
CC
or GND
[7]
- 0.04 0.4 mA
C
I
input capacitance V
I
= 0 V or V
CC
-3-pF
C
O
output capacitance V
I/O
= 0 V or 3.0 V - 9 - pF
V
CC
= 3.3 V ± 0.3 V
[8]
V
IK
input clamping voltage V
CC
= 3.0 V; I
IK
= −18 mA - −0.85 −1.2 V
V
OH
HIGH-level output voltage V
CC
= 3.0 V to 3.6 V; I
OH
= −100 µAV
CC
− 0.2 V
CC
-V
V
CC
= 3.0 V; I
OH
= −32 mA 2.0 2.3 - V
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 10 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
[1] All typical values are at V
CC
= 2.5 V and T
amb
= 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at V
CC
or GND.
[4] Not guaranteed.
[5] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
=1.2VtoV
CC
= 2.5 V ± 0.2 V
a transition time of 100 µs is permitted. This parameter is valid for T
amb
=25°C only.
[6] I
CC
is measured with outputs pulled up to V
CC
or pulled down to ground.
[7] This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
[8] All typical values are at V
CC
= 3.3 V and T
amb
= 25 °C.
[9] This is the bus hold overdrive current required to force the input to the opposite logic state.
V
OL
LOW-level output voltage V
CC
= 3.0 V; I
OL
= 100 µA - 0.07 0.2 V
V
CC
= 3.0 V; I
OL
= 16 mA - 0.25 0.4 V
V
CC
= 3.0 V; I
OL
= 32 mA - 0.3 0.5 V
V
CC
= 3.0 V; I
OL
= 64 mA - 0.4 0.55 V
V
OL(pu)
power-up LOW-level output
voltage
V
CC
= 3.6 V; I
O
= 1 mA;
V
I
=V
CC
or GND
[2]
- - 0.55 V
I
LI
input leakage current
control pins V
CC
= 3.6 V; V
I
= V
CC
or GND - 0.1 ±1 µA
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V - 0.1 10 µA
I/O data pins V
CC
= 3.6 V; V
I
=V
CC
[3]
- 0.5 1 µA
V
CC
= 3.6 V; V
I
= 0 V
[3]
- +0.1 −5 µA
I
OFF
off current V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V - 0.1 ±100 µA
I
HOLD
bus hold current data inputs V
CC
= 3 V; V
I
= 0.8 V 75 130 - µA
V
CC
= 3 V; V
I
= 2.0 V −75 −140 - µA
V
CC
= 3.6 V; V
I
= 0V to 3.6 V
[9]
±500 - - µA
I
EX
external current into output output HIGH-state when V
O
>V
CC
;
V
O
= 5.5 V; V
CC
= 3.0 V
- 10 125 µA
I
PU
power-up 3-state output
current
V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
[10]
-1±100 µA
I
PD
power-down 3-state output
current
V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
[10]
-1±100 µA
I
OZ
3-state output current V
CC
= 3.6 V; V
I
= V
IL
or V
IH
output HIGH state; V
O
= 3.0 V - 0.5 5 µA
output LOW-state; V
O
= 0.5 V - +0.5 −5 µA
I
CC
quiescent supply current V
CC
= 3.6 V; V
I
= GND or V
CC
; I
O
= 0 A
outputs HIGH-state - 0.06 0.1 mA
outputs LOW-state - 3.9 5.5 mA
outputs disabled
[6]
- 0.06 0.1 mA
∆I
CC
additional quiescent supply
current per input pin
V
CC
= 3 V to 3.6 V; one input at
V
CC
− 0.6 V, other inputs at V
CC
or GND
[7]
- 0.04 0.4 mA
C
I
input capacitance V
I
= 0 V or V
CC
-3-pF
C
O
output capacitance V
I/O
= 0 V or 3.0 V - 9 - pF
Table 7: Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T
amb
=
−
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ Max Unit
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 11 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
[10] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
=1.2VtoV
CC
= 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for T
amb
=25°C only.
11. Dynamic characteristics
Table 8: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10;
T
amb
=
−
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ Max Unit
V
CC
= 2.5 V ± 0.2 V
[1]
f
max
maximum clock frequency see Figure 5 150 - - MHz
t
PLH
propagation delay nCP to nQx see Figure 5 1.5 2.9 4.5 ns
t
PHL
HIGH-to-LOW propagation delay
nCP to nQx see
Figure 5 1.4 2.7 4.2 ns
n
MR to nQx see Figure 7 1.5 2.7 4.2 ns
t
PZH
output enable time to HIGH-level see Figure 8 2.1 3.4 5.0 ns
t
PZL
output enable time to LOW-level see Figure 9 1.8 3.0 4.7 ns
t
PHZ
output disable time from HIGH-level see Figure 8 1.7 3.0 4.3 ns
t
PLZ
output disable time from LOW-level see Figure 9 1.4 2.3 3.3 ns
t
su(H)
set-up time HIGH
nDx to nCP see
Figure 6 1.0 0.5 - ns
n
CE to nCP see Figure 6 1.0 0.2 - ns
t
su(L)
set-up time LOW
nDx to nCP see
Figure 6 1.8 1.3 - ns
n
CE to nCP see Figure 6 +0.5 −0.1 - ns
t
h(H)
hold time HIGH
nDx to nCP see
Figure 6 +0.1 −1.4 - ns
n
CE to nCP see Figure 6 1.0 0.2 - ns
t
h(L)
hold time LOW
nDx to nCP see
Figure 6 +0.1 −0.5 - ns
n
CE to nCP see Figure 6 +1.0 −0.1 - ns
t
WH
pulse width HIGH nCP see Figure 5 2.0 0.8 - ns
t
WL
pulse width LOW
nCP see
Figure 5 3.0 2.1 - ns
n
MR see Figure 7 2.0 0.8 - ns
t
rec
recovery time nMR to nCP see Figure 7 2.0 1.3 - ns
V
CC
= 3.3 V ± 0.3 V
[2]
f
max
maximum clock frequency see Figure 5 250 - - MHz
t
PLH
propagation delay nCP to nQx see Figure 5 1.0 2.3 3.1 ns
t
PHL
HIGH-to-LOW propagation delay
nCP to nQx see
Figure 5 1.0 2.1 2.9 ns
n
MR to nQx see Figure 7 1.0 2.3 2.9 ns
t
PZH
output enable time to HIGH-level see Figure 8 1.7 2.7 4.0 ns
t
PZL
output enable time to LOW-level see Figure 9 1.4 2.3 3.5 ns
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74ALVT16823DGGY

Mfr. #:
Buy 74ALVT16823DGGY
Manufacturer:
Nexperia
Description:
Flip Flops 18-Bit Bus-Interface D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
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