74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 12 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
[1] All typical values are measured at V
CC
= 2.5 V and T
amb
= 25 °C.
[2] All typical values are measured at V
CC
= 3.3 V and T
amb
= 25 °C.
12. Waveforms
t
PHZ
output disable time from HIGH-level see Figure 8 2.2 3.1 4.0 ns
t
PLZ
output disable time from LOW-level see Figure 9 1.8 2.6 3.5 ns
t
su(H)
set-up time HIGH
nDx to nCP see
Figure 6 1.0 0.5 - ns
n
CE to nCP see Figure 6 1.0 0.1 - ns
t
su(L)
set-up time LOW
nDx to nCP see
Figure 6 1.6 1.1 - ns
n
CE to nCP see Figure 6 +0.5 0.5 - ns
t
h(H)
hold time HIGH
nDx to nCP see
Figure 6 +0.1 0.7 - ns
n
CE to nCP see Figure 6 1.0 0.5 - ns
t
h(L)
hold time LOW
nDx to nCP see
Figure 6 +0.1 0.5 - ns
n
CE to nCP see Figure 6 +1.0 0.1 - ns
t
WH
pulse width HIGH nCP see Figure 5 1.5 0.7 - ns
t
WL
pulse width LOW
nCP see
Figure 5 2.5 1.4 - ns
n
MR see Figure 7 2.0 1.5 - ns
t
rec
recovery time nMR to nCP see Figure 7 2.0 1.1 - ns
Table 8: Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10;
T
amb
=
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Measurement points are given in Table 9.
V
OH
is a typical voltage output drop that occur with the output load.
Fig 5. Propagation delay, clock input to output, clock pulse width and maximum clock
frequency
V
M
V
M
V
M
t
PLH
t
PHL
t
WH
t
WL
1/f
max
V
M
input nCP
output nQx
0 V
V
I
0 V
V
OH
001aad399
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 13 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 6. Data set-up and hold times
Measurement points are given in Table 9.
V
OH
is a typical voltage output drop that occur with the output load.
Fig 7. Master reset pulse width, master reset to output delay and master reset to clock
recovery time
Measurement points are given in Table 9.
V
OH
is a typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level
001aad401
V
M
input nDx,
nCE
input nCP
V
M
V
M
V
M
V
M
V
M
t
su(H)
t
h(H)
t
su(L)
t
h(L)
0 V
0 V
V
I
V
I
input nMR
input nCP
output nQx
t
PHL
t
WL
t
REC
V
M
0 V
V
OH
0 V
0 V
V
M
V
M
V
M
001aad400
V
I
V
I
001aad402
V
M
V
Y
V
M
t
PHZ
t
PZH
V
M
V
OH
0 V
0 V
input nOE
output nQx
V
I
74ALVT16823_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 2 August 2005 14 of 20
Philips Semiconductors
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Measurement points are given in Table 9.
V
OL
is a typical voltage output drop that occur with the output load.
Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level
Table 9: Measurement points
Supply voltage Input Output
V
M
V
M
V
X
V
Y
3 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
2.7 V 0.5 × V
CC
0.5 × V
CC
V
OL
+ 0.3 V V
OH
0.3 V
001aad404
input nOE
V
M
V
M
V
X
t
PLZ
t
PZL
output nQx V
M
0 V
V
OL
V
I
V
I

74ALVT16823DGGY

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops 18-Bit Bus-Interface D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
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