4
FN8127.4
November 12, 2015
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET
pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When V
CC
exceeds the device V
TRIP
value for
200ms (nominal) the circuit releases RESET
, allowing the
processor to begin executing code. While V
CC
< V
TRIP
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the V
CC
level and
asserts RESET
if supply voltage falls below a preset
minimum V
TRIP
. The RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET
signal remains active until the voltage
drops below 1V. It also remains active until V
CC
returns and
exceeds V
TRIP
for 200ms.
When V
CC
falls below V
TRIP
, any communications in
progress are terminated and communications are inhibited
until V
CC
exceeds V
TRIP
for t
PURST
.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS
/WDI pin periodically to prevent a RESET signal. The
CS
/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
V
CC
Threshold Reset Procedure
The X5083 is shipped with a standard V
CC
threshold (V
TRIP
)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
TRIP
is not exactly right, or if higher precision is
needed in the V
TRIP
value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the V
CC
pin and tie the WP pin to the
programming voltage V
P
. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS
going
HIGH on the write operation initiates the V
TRIP
programming
sequence. Bring WP
LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native” voltage
level. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
must be 4.0V, then the V
TRIP
must be reset. When
V
TRIP
is reset, the new V
TRIP
is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the Vcc pin and tie the WP
pin to the
programming voltage V
P
. Then send a WREN command,
followed by a write of data 00h to address 03h. CS
going
HIGH on the write operation initiates the V
TRIP
programming
sequence. Bring WP
LOW to complete the operation.
Note: This operation also writes 00h to array address 03h.
X5083
5
FN8127.4
November 12, 2015
01234567
SCK
SI
CS
06h
012345678910 20 21 22 23
16 Bits
0001h
02h
WP
V
P
= 15-18V
00h
WREN Write Address Data
FIGURE 1. SET V
TRIP
LEVEL SEQUENCE (V
CC
= DESIRED V
TRIP
VALUE)
01234567
SCK
SI
CS
06h
012345678910 20 21 22 23
16 Bits
0003h
02h
WP
V
P
= 15-18V
00h
WREN
Write
Address
Data
FIGURE 2. RESET V
TRIP
LEVEL SEQUENCE (V
CC
> 3V. WP = 15-18V)
1
2
3
4
8
7
6
5
X5083
V
TRIP
Adj.
V
P
RESET
4.7K
SI
SO
CS
SCK
µC
Adjust
Run
FIGURE 3. SAMPLE V
TRIP
RESET CIRCUIT
X5083
6
FN8127.4
November 12, 2015
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
RESET pin
goes active?
Measured V
TRIP
-
Desired V
TRIP
DONE
Execute
Sequence
Reset V
TRIP
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Sequence
Set V
TRIP
New V
CC
Applied =
Old V
CC
Applied + Error
(V
CC
= V
CC
- 50mV)
Execute
Sequence
Reset V
TRIP
New V
CC
Applied =
Old V
CC
Applied - Error
Error
–Emax
–Emax < Error < Emax
YES
NO
Error
Emax
Emax = Maximum Desired Error
FIGURE 4. V
TRIP
PROGRAMMING SEQUENCE
X5083

X5083S8IZ-2.7AT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 8K SPI EE RST LW 2 7-3 6V
Lifecycle:
New from this manufacturer.
Delivery:
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