8
FN8127.4
November 12, 2015
Watchdog Timer
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction. A change to the
Watchdog Timer, either setting a new time out period or
turning it off or on, takes effect, following either the next
command (read or write) or cycling the power to the device.
The recommended procedure for changing the Watch-dog
Timer settings is to do a WREN, followed by a write status
register command. Then execute a soft-ware loop to read
the status register until the MSB of the status byte is zero. A
valid alternative is to do a WREN, followed by a write status
register command. Then wait 10ms and do a read status
command.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS
high. Refer to the read EEPROM array sequence
(Figure 5).
To read the status register, the CS
line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 6).
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS
is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS
must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS
must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the same page and overwrite any data that
may have been previously written.
For a write operation (byte or page write) to be completed,
CS
can only be brought HIGH after bit 0 of the last data byte
to be written is clocked in. If it is brought HIGH at any other
time, the write operation will not be completed (Figure 8).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 5, 6
and 7 must be “0”.
Read Status Operation
If there is not a nonvolatile write in progress, the read status
instruction returns the block lock setting from the status
register which contains the watchdog timer bits WD1, WD0,
and the block lock bits IDL2-IDL0 (Figure 6). The block lock
bits define the block lock condition (Table 1). The watchdog
timer bits set the operation of the watchdog timer (Table 2).
The other bits are reserved and will return ’0’ when read. See
Figure 6.
During an internal nonvolatile write operaiton, the Read
Status Instruction returns a HIGH on SO in the first bit
following the RDSR instruction (the MSB). The remaining
bits in the output status byte are undefined. Repeated Read
Status Instructions return the MSB as a ‘1’ until the
nonvolatile write cycle is complete. When the nonvolatile
write cycle is completed, the RDSR instruction returns a ‘0’
in the MSB position with the remaining bits of the status
register undefined. Subsequent RDSR instructions return
the Status Register Contents. See Figure 10.
RESET Operation
The RESET output is designed to go LOW whenever V
CC
has dropped below the minimum trip point and/or the
watchdog timer has reached its programmable time out limit.
The RESET
output is an open drain output and requires a
pull up resistor.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS
is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• Reset signal is active for t
PURST
.
TABLE 2. WATCHDOG TIMER DEFINITION
STATUS REGISTER BITS
WATCHDOG TIME OUT
(TYPICAL)WD1 WD0
0 0 1.4s
0 1 600ms
1 0 200ms
1 1 disabled (factory default)
X5083
