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NCN5193MNTWG

P1-P3P4-P6P7-P9P10-P12P13-P14
NCN5193
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10
Rx comparator. The ON Semiconductor LM285D 1.235 V
reference is recommended.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
detect to a nominal 100 mV
p-p
.
Bias Current Resistor
The NCN5193 requires a bias current resistor R
BIAS
to be
connected between CBIAS and V
SS
. The bias current
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 10 mA.
BIAS
CBIAS
OPA
AREF
10 mA
R
BIAS
PC20101118 .4
Figure 10. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
R
BIAS
+
AREF
10 mA
The recommended bias current resistor is 120 KW when
AREF is equal to 1.235 V.
Oscillator
The clock signal used by NCN5193 can either be
460.8 kHz, 921.6 kHz, 1.8432 MHz or 3.6864 MHz. This
can be provided by an external clock or a resonator or crystal
connected to the internal oscillator. This is selected by
connecting pin 27 to VDD (for external oscillator) or VSS
(for internal oscillator). The correct divider value must be
chosen so that the internal system clock is always 460.8 kHz.
This divider value can be set in the Clock Configuration
Register (CCR), bits 1−0. In the CCR, divider values can
also be chosen for the CLK1 and CLK2 outputs. These
values can be freely chosen and do not affect operation of the
HART transceiver.
Internal Oscillator Option
The oscillator cell will function with a 460.8 kHz,
921.6 kHz, 1.8432 MHz or 3.6864 MHz crystal or ceramic
resonator. A parallel resonant ceramic resonator can be
connected between XIN and XOUT. Figure 11 illustrates the
crystal option for clock generation using a 460.8 kHz (±1%
tolerance) parallel resonant crystal and two tuning
capacitors C
x
. The actual values of the capacitors may
depend on the recommendations of the manufacturer of the
resonator. Typically, capacitors in the range of 10 pF to
470 pF are used. Additionally, a resistor may be required
between XOUT and the crystal terminal, depending on
manufacturer recommendation.
XOUT
XIN
C
X
C
X
460.8 kHz
Crystal
Oscillator
PC20101118.5
Figure 11. Crystal Oscillator
External Clock Option
It may be desirable to use an external clock as shown in
Figure 12 rather than the internal oscillator. In addition, the
NCN5193 consumes less current when an external clock is
used. Minimum current consumption occurs with the clock
connected to XOUT and XIN connected to V
SS
.
XOUT
XIN
Crystal
Oscillator
PC20101118 .6
460.8 kHz
Figure 12. Oscillator with External Clock
Reset
The NCN5193 modem includes a Power on Reset block.
An external resistor division of the supply voltage is
required, and should be tied to pin VPOR. This pin is
attached to an internal comparator, and is compared to the
AREF voltage. When this comparator trips, the RESETB
pin will be pulled low and the IC will reset. After VPOR
returns to a valid level, the RESETB pin will be held low for
at least an additional 35 ms (may be longer depending on
clock frequency). The RESETB pin will also be pulled low
when a failure is detected by the watchdog timer. When the
microcontroller fails to provide a periodical kick signal,
either by a pulse on the kick pin or by an update to the
sigma−delta register (configurable in the GCR), the
watchdog will pull down the RESETB pin for 140 ms. A kick
signal should be provided to the IC at least every 53 ms. The
watchdog timer can also guard against system clock failures
if bit 2 of the GCR is set. In this case, the RESETB pin will
also be pulled low when the system clock frequency is
outside of 0.5x − 2x the nominal frequency (460.8 kHz).
NCN5193
www.onsemi.com
11
POR
VPOR
OPA
AREF
KVDE20110408 .1
VDD
Figure 13. Power on Reset Block
Figure 14. SPI Frame
b7
SCLK
CS
DATA
b6 b5 b4 b3 b2 b1 b0
Byte 0
76543210
0 Address10 0
Byte 1
76543210
W15−W8 for Reg 1, 2, 3
Byte 2
76543210
W7−W0 for Reg 1, 2, 3
76543210
W23−W16 for Reg A
76543210
W15−W8 for Reg A
76543210
W7−W0 for Reg A
Byte 3
Figure 15. Register Write Format
SPI Communication
The SPI bus on the NCN5193 is made up of three signals;
DATA, SCLK, and CS operating in SPI mode 1 (CPOL = 0,
CPHA = 1, as shown in Figure 14).
CS should first go high at least one clock cycle before the
other signals change. One clock cycle is 2.17 ms at a master
clock frequency of 460.8 kHz.
SCLK can begin to clock in DATA serially to the chip on
the falling edge of SCLK. SCLK should have a maximum
frequency of 460.8 kHz. The format of the data should be
most significant bit first.
DATA is shifted into the chip on the falling edge of SCLK,
and thus for correct operation DATA should change only on
the rising edge of SCLK. The first bit shifted in is the MSB.
Once the data is shifted in, CS should go low no sooner than
one clock cycle after the last rising edge of the last byte of
SCLK. To write to a register, first a command byte must be
sent which includes the register address (as shown in Figure
15), followed by 2 bytes (for GCR, CCR, and ACR) or 3
bytes (for SDR) of data. When writing data to the GCR,
CCR, or ACR registers, the first byte must be the bitwise
inverse of the configuration data in the second byte.
Internal Registers
The NCN5193 has four registers to setup its internal
operation. In Tables 10 to 16 an explanation of their usage
is given, together with their reset values.
Table 10. GENERAL CONFIGURATION REGISTER (GCR)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01
Reset 1 0 0 0 0 1 0 1
Data - - - RXD_IDLE - WDT_CLK WDT_KICK
The general configuration register is used to set the RxD idle state, enable or disable the monitoring of the system clock and
setting the watchdog timer kick source. A write to this register should always be preceded with an inverted value to the shadow
register.
Table 11. GENERAL CONFIGURATION REGISTER PARAMETERS
Parameter Value Description Info
RXD_IDLE
0 Low
Sets the idle state for the RxD pin (when CD is low)
1 High
WDT_CLK
0 Enable
Disable/Enable monitoring of the clock frequency by the watchdog timer.
1 Disable
WDT_KICK
00 Disable Kick signal to watchdog timer is disabled
01 External Watchdog kick source is a pulse on the KICK pin
10
Sigma-Delta Watchdog kick source is an write to the Sigma-Delta Data register (SDR)
11
NCN5193
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12
Table 12. CLOCK CONFIGURATION REGISTER (CCR)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02
Reset 1 0 1 1 0 1 1 1
Data CLK2_DIV CLK1_DIV SYSCLK_DIV
The clock configuration register is used to set the correct division ratios for both clock outputs and the system clock. A write
to this register should always be preceded with an inverted value to the shadow register.
Table 13. CLOCK CONFIGURATION REGISTER PARAMETERS
Parameter Value Description Info
CLK2_DIV
000 Divide by 1
Set the clock division value for clock output 2 (CLK2) with regard to the
oscillator frequency.
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 8
110 Divide by 16
111 Divide by 32
CLK1_DIV
000 Divide by 1
Set the clock division value for clock output 1 (CLK1) with regard to the
oscillator frequency.
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 8
110 Divide by 16
111 Divide by 32
SYSCLK_DIV
00 Divide by 1
Set the clock division value for the system clock with regard to the oscil-
lator frequency. These bits must be set so the system clock is 460.8 kHz
01
Divide by 2
10 Divide by 4
11 Divide by 8
Table 14. ANALOG CONFIGURATION REGISTER – ACR
General Configuration Register (GCR)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x03
Reset 1 1 1 1 1 1 0 1
Data MOD_EN RXAMP_EN RXCMP_EN CDCMP_EN TXAMP_EN MODDAC_EN WDOSC_EN SDDAC_EN
The analog configuration register is used to enable or disable various analog blocks. A write to this register should always
be preceded with an inverted value to the shadow register.
P1-P3P4-P6P7-P9P10-P12P13-P14

NCN5193MNTWG

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Manufacturer:
ON Semiconductor
Description:
Interface - Specialized NCN5193
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