Rev. 1.4 6/18 Copyright © 2018 by Silicon Laboratories Si595
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10
TO 810 MHZ
Features
Applications
Description
The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si595 is available with
any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs,
where a different crystal is required for each output frequency, the Si595
uses one fixed crystal to provide a wide range of output frequencies. This IC-
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides supply noise rejection, simplifying the task of generating low-jitter
clocks in noisy environments. The Si595 IC-based VCXO is factory-
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, tuning slope, and absolute pull range (APR).
Specific configurations are factory programmed at time of shipment, thereby
eliminating the long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 to 810 MHz
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry standard 5x7 and
3.2x5 mm packages
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
FTTx
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–810 MHz
DSPLL
®
Clock Synthesis
ADC
V
DD
CLK+CLK–
Vc
OE GND
Ordering Information:
See page 9.
Pin Assignments:
See page 8.
(Top View)
Si5602
1
2
3
6
5
4
V
C
GND
OE
V
DD
CLK+
CLK–
Si595
REVISION D
Si595
2 Preliminary Rev. 1.4
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Package Outline Drawing: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7. PCB Land Pattern: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
8. Si5xx Mark Specification: 5x7mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
9. Si5xx Mark Specification: 3.2 x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Si595
Rev. 1.4 3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage
1
V
DD
3.3 V option 2.97 3.3 3.63
V2.5 V option 2.25 2.5 2.75
1.8 V option 1.71 1.8 1.89
Supply Current I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
120
110
100
90
135
120
110
100
mA
Tristate mode 60 75
Output Enable (OE)
2
V
IH
0.75 x V
DD
——
V
V
IL
——0.5
Operating Temperature Range T
A
–40 85 °C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 9 for further details.
2. OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 9.
Table 2. V
C
Control Voltage Input
Parameter Symbol Test Condition Min Typ Max Units
Control Voltage Tuning Slope
1,2,3
K
V
10 to 90% of V
DD
—45
95
125
185
380
ppm/V
Control Voltage Linearity
4
L
VC
BSL –5 ±1 +5
%
Incremental –10 ±5 +10
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
V
C
Input Impedance Z
VC
500 k
V
C
Input Capacitance C
VC
—50pF
Nominal Control Voltage V
CNOM
@ f
O
—V
DD
/2 V
Control Voltage Tuning Range V
C
0V
DD
V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 9.
2. For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3. K
V
variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.

595ND70M6560DGR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
VCXO Oscillators Differential/single-ended single frequency VCXO; 10-810 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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