2010-2015 Microchip Technology Inc. DS30009622M-page 5
PIC18F2XXX/4XXX FAMILY
The following devices are included in 44-pin QFN parts:
FIGURE 2-5: 44-PIN QFN
2.3 Memory Maps
For PIC18FX6X0 devices, the code memory space extends from 0000h to 0FFFFh (64 Kbytes) in four 16-Kbyte blocks.
For PIC18FX5X5 devices, the code memory space extends from 0000h to 0BFFFFh (48 Kbytes) in three 16-Kbyte
blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block
0. All of these blocks define code protection boundaries within the code memory space.
The size of the Boot Block in PIC18F2585/2680/4585/4680 devices can be configured as 1, 2 or 4K words (see
Figure 2-6). This is done through the BBSIZ<1:0> bits in the Configuration register, CONFIG4L. It is important to note
that increasing the size of the Boot Block decreases the size of Block 0.
• PIC18F4221 • PIC18F4523
• PIC18F4321 • PIC18F4525
• PIC18F4410 • PIC18F4550
• PIC18F4420 • PIC18F4553
• PIC18F4423 • PIC18F4580
• PIC18F4450 • PIC18F4585
• PIC18F4455 • PIC18F4610
• PIC18F4458 • PIC18F4620
• PIC18F4480 • PIC18F4680
• PIC18F4510 • PIC18F4682
• PIC18F4520 • PIC18F4685
• PIC18F4515
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4XXX
37
RA3
RA2
RA1
RA0
MCLR
/VPP/RE3
RB7/PGD
RB6/PGC
RB5/PGM
NC
RC6
D+/VP
D-/VM
RD3
RD2
RD1
RD0
V
USB
RC2
RC1
RC0
OSC2
OSC1
V
SS
AVDD
RA5
RA4
RC7
RD4
RD5
RD6
V
SS
VDD
RB0
RB1
RB2
RB3
RD7
5
4
AV
SS
VDD
AVDD
RB4
RE0
RE1
RE2
