ZL30119 Data Sheet
13
Zarlink Semiconductor Inc.
1.2 DPLL Mode Control
Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The
mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30119 will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized.
Reset
Another reference is
qualified and available
for selection
Phase lock on
the selected
reference is
achieved
Lock
Acquisition
Normal
(Locked)
No references are
qualified and
available for
selection
Free-Run
Holdover
Selected reference
fails
All references are monitored
for frequency accuracy and
phase regularity, and at least
one reference is qualified.
Normal
(Locked)