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ZL30119GGG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
ZL30119 Data Sheet
16
Zarlink Semiconductor Inc.
Coarse Frequency Monitor (CFM)
The CFM block monitors the reference frequency over a measurement period of 30 μs so that it can quickly detect
large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%
or approximately 30000 ppm.
Precise Frequency Monitor (PFM)
The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an
accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities
are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the
rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the
edge of the acceptance range.
When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output
frequency (f
ocsi
) as its point of reference.
Guard Soak Timer (GST)
The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the
SCM blocks and applying a selectable rate of decay when no failures are detected.
As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper
threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator
decrements until it reaches its lower threshold during the qualification window.
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures
All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference
clock cycles within the frame pulse period.
1.5 Output Clocks and Frame Pulses
The ZL30119 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n,
diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks and four programmable LVCMOS
(p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH
frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also
available.
ref
CFM or SCM failures
upper threshold
lower threshold
t
d
- disqualification time
t
q
- qualification time = n * t
d
t
d
t
q
gst_fail
ZL30119 Data Sheet
17
Zarlink Semiconductor Inc.
The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30119 to have two independent timing paths.
Figure 6 - Output Clock Configuration
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
diff0_p/n,
diff1_p/n
(LVPECL)
sdh_clk0,
sdh_clk1
(LVCMOS)
p0_clk0, p1_clk0
(LVCMOS)
p0_clk1, p1_clk1
(LVCMOS)
sdh_fp0, shd_fp1,
p0_fp0, p0_fp1
(LVCMOS)
6.48 MHz 6.48 MHz 2 kHz p
x
_clk0
p
x
_clk1 =
2
M
166.67 Hz
(48x 125 μs frames)
19.44 MHz 9.72 MHz N * 8 kHz (up to
77.76 MHz)
400 Hz
38.88 MHz 12.96 MHz 1 kHz
51.84 MHz 19.44 MHz 2 kHz
77.76 MHz 25.92 MHz 4 kHz
155.52 MHz 38.88 MHz 8 kHz
311.04 MHz 51.84 MHz 32 kHz
622.08 MHz 77.76 MHz 64 kHz
Table 4 - Output Clock and Frame Pulse Frequencies
DPLL2
p0_clk0
p0_fp0
p0_clk1
p0_fp1
P0
Synthesizer
DPLL1
p1_clk0
p1_clk1
P1
Synthesizer
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
SONET/SDH
APLL
diff0
diff1
Feedback
Synthesizer
fb_clk
ZL30119 Data Sheet
18
Zarlink Semiconductor Inc.
1.6 Configurable Input-to-Output and Output-to-Output Delays
The ZL30119 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag
the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with
a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative
values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are
unaffected by this delay adjustment.
In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the
ability to add their own fine delay adjustments using the P0 Fine Delay, P1 Fine Delay, and SDH Fine Delay.
These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be
independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs
can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses
(SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay.
Figure 7 - Phase Delay Adjustments
DPLL1
DPLL2
P0 Fine Delay
p0_clk0
p0_clk1
p0_fp0
p0_fp1
P0
Synthesizer
Coarse Delay
Coarse Delay
FP Delay
FP Delay
fb_clk
p1_clk0
p1_clk1
P1 Fine Delay
Diff Delay
Diff Delay
diff0
diff1
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
SDH Fine Delay
Feedback
Synthesizer
DPLL1 Fine Delay
Coarse Delay
Coarse Delay
FP Delay
FP Delay
Coarse Delay
Coarse Delay
P1
Synthesizer
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

ZL30119GGG2

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Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free Low Jitter Linecard Synchronizer
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