ZL30119 Data Sheet
22
Zarlink Semiconductor Inc.
36 p0_enable 8F Control register to enable p0_clk0, p0_clk1,
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
R/W
37 p0_run 0F Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
R/W
38 p0_freq_0 00 Control register for the [7:0] bits of the N of
N*8k clk0
R/W
39 p0_freq_1 01 Control register for the [13:8] bits of the N of
N*8k clk0
R/W
3A p0_clk0_offset90 00 Control register for the p0_clk0 phase position
coarse tuning
R/W
3B p0_clk1_div 3E Control register for the p0_clk1 frequency
selection
R/W
3C p0_clk1_offset90 00 Control register for the p0_clk1 phase position
coarse tuning
R/W
3D p0_offset_fine 00 Control register for the output/output phase
alignment fine tuning for p0 path
R/W
3E p0_fp0_freq 05 Control register to select the p0_fp0 frame
pulse frequency
R/W
3F p0_fp0_type 83 Control register to select fp0 type R/W
40 p0_fp0_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
41 p0_fp0_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
42 p0_fp0_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
43 p0_fp1_freq 05 Control register to select p0_fp1 frame pulse
frequency
R/W
44 p0_fp1_type 11 Control register to select fp1 type R/W
45 p0_fp1_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
46 p0_fp1_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
47 p0_fp1_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
P1 Configuration Registers
48 p1_enable 83 Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
R/W
49 p1_run 03 Control register to generate enable/disable
p1_clk0 and p1_clk1
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)