FEBRUARY 8, 2017 13 2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0242 / 9DBL0252 DATASHEET
SMBus Table: Stop State and Impedance Control
Byte 11 Name Control Function Type 0 1 Default
Bit 7
FB_imp[1] FB Zout RW 00=33 DIF Zout 10=100 DIF Zout
Bit 6
FB_imp[0] FB Zout RW 01=85 DIF Zout 11 = Reserved
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
STP[1] RW 00 = Low/Low 10 = High/Low 0
Bit 0
STP[0] RW 01 = HiZ/HiZ 11 = Low/High 0
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 12 Name Control Function Type 0 1 Default
Bit 7
DIF0_imp[1] RW 00=33 DIF Zout 10=100 DIF Zout
Bit 6
DIF0_imp[0] RW 01=85 DIF Zout 11 = Reserved
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 13 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
DIF1_imp[1] DIF1 Zout RW 00=33 DIF Zout 10=100 DIF Zout
Bit 0
DIF1_imp[0] DIF1 Zout RW 01=85 DIF Zout 11 = Reserved
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 14 Name Control Function Type 0 1 Default
Bit 7
OE0_pu/pd[1] RW 00=None 10=Pup 0
Bit 6
OE0_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
see Note
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
see Note
Reserved
OE0 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
Reserved
Reserved
Reserved
DIF0 Zout
see Note
True/Complement DIF Output
Disable State
Reserved
Reserved
Reserved
Reserved
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 14 FEBRUARY 8, 2017
9DBL0242 / 9DBL0252 DATASHEET
SMBus Table: Pull-up Pull-down Control
Byte 15 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
OE1_pu/pd[1] RW 00=None 10=Pup 0
Bit 0
OE1_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Note: These values are for xx42, and xx52. P2 is factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 16 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
X
Bit 2
X
Bit 1
CKPWRGD_PD_pu/pd[1] RW 00=None 10=Pup 1
Bit 0
CKPWRGD_PD_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 0
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
Byte s 17 i s Re se rve d
SMBus Table: Polarity Control
Byte 18 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
OE1_polarity Sets OE1 polarity RW Enabled when Low Enabled when High 0
Bit 3
OE0_polarity Sets OE0 polarity RW Enabled when Low Enabled when High 0
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Polarity Control
Byte 19 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
CKPWRGD_PD
Determines
CKPWRGD_PD polarity
RW
Power Down when
Low
Power Down when
High
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CKPWRGD_PD Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
FEBRUARY 8, 2017 15 2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0242 / 9DBL0252 DATASHEET
Marking Diagrams
Notes:
1. “LOT” is the lot sequence number.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. Line 2: truncated part number
4. “I” denotes industrial temperature range device.
Thermal Characteristics
LOT
242BI
YYWW
LOT
252BI
YYWW
LOT
2B000
YYWW
PARAMETER SYMBOL CONDITIONS PKG
TYP
VALUE
UNITS NOTES
Θ
J
C
Junction to Case 62 °
C/W
1
Θ
Jb
Junction to Base 5.4 °
C/W
1
Θ
JA0
Junction to Air, still air 50 °
C/W
1
Θ
JA1
Junction to Air, 1 m/s air flow 43 °
C/W
1
Θ
JA3
Junction to Air, 3 m/s air flow 39 °
C/W
1
Θ
JA5
Junction to Air, 5 m/s air flow 38 °
C/W
1
1
ePad soldered to board
Thermal Resistance
NLG20
NLG24

9DBL0252BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 3.3V LP-HCSL PCIE ZDB FOB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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