2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 18 FEBRUARY 8, 2017
9DBL0242 / 9DBL0252 DATASHEET
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
“xxx” is a unique factory assigned number to identify a particular default configuration.
Revision History
Part / Order Number Notes Shipping Packaging Package Temperature
9DBL0242BKILF Tubes 24-pin VFQFPN -40 to +85° C
9DBL0242BKILFT Tape and Reel 24-pin VFQFPN -40 to +85° C
9DBL0252BKILF Tubes 24-pin VFQFPN -40 to +85° C
9DBL0252BKILFT Tape and Reel 24-pin VFQFPN -40 to +85° C
9DBL02P2BxxxKILF Tubes 24-pin VFQFPN -40 to +85° C
9DBL02P2BxxxKILFT Tape and Reel 24-pin VFQFPN -40 to +85° C
100Ω
85Ω
Factory configurable.
Contact IDT for
addtional information.
Rev. Initiator Issue Date Description Page #
A RDW 5/26/20106
1. Updated all electrical tables with char data, changed additive phase
jitter frequency from 125M to 156.25MHz and move to final.
2. Updated front page text
3. Updated default value of Byte 0 from 38 hex to 18 hex
4. Updated default value of Byte 5 from 01 hex to 11 hex
5. Indicated that Byte 6 is Read/Write
6. Update DS title
Various
B RDW 5/27/2016
1. Changed '1' value in Byte 0 to indicate "Pin Control"
2. Stylistic update to block diagram
3. Minor updates to SMBus registers 0 and 1 for Readability
4. Corrected Byte 11 description for the '10' and '11' cases.
5. Front page text update for family consistency.
6. Updated ordering information.
Various
C RDW 5/31/2016 1. Minor corrections to Byte 1 [1:0] and Byte 11 [1:0]
D RDW 6/8/2016
1. Electrical Table and SMBus Updates/Corrections
2. Release to final.
Various
E RDW 10/6/2016 1. Slight updates to PCIe SRIS Spec table to reflect PCI SIG Updates 9
F RDW 2/8/2017 Renamed datasheet to 9DBL0242/9DBL0252 Various
