2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 8 FEBRUARY 8, 2017
9DBL0242 / 9DBL0252 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode (100MHz) 2 3.3 4 MHz 1,5
-3dB point in Low BW Mode (100MHz) 1 1.5 2 MHz 1,5
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain (100MHz) 0.8 2 dB 1
Duty Cycle t
D
Measured differentially, PLL Mode 45 50 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode -1 0.0 1 % 1,3
t
dBYP
= 50% 2500 3406 4500 ps 1
t
dPLL
= 50% -100 8 100 ps 1,4
Skew, Output to Output t
sk3
= 50% 21 55 ps 1,4
PLL mode 15 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 1 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
PLL Bandwidth BW
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT
hPCIeG1-CC
PCIe Gen 1 23 32 86 ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.6 0.8 3
ps
(rms)
1,2,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
1.7
2.1 3.1
ps
(rms)
1,2,5
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.4
0.48 1
ps
(rms)
1,2,5
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.4
0.48 0.5
ps
(rms)
1,2,5
t
jphPCIeG1-CC
PCIe Gen 1 0.0 0.01
ps
(p-p)
1,2,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.0 0.01
ps
(rms)
1,2,4,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.0 0.01
ps
(rms)
1,2,4,5
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
(rms)
1,2,4,5
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0 0.01
ps
(rms)
1,2,4,5
1
Applies to all outputs.
5
Driven by 9FGL0841 or equivalent
3
Sample size of at least 100K cycles. This fi
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
For RMS values additive jitter is calculated by solvin
the followin
equation for b [a^2+b^2=c^
] where a is rms input jitter and c is rms total jitter.
Phase Jitter,
PLL Mode
t
jphPCIeG2-CC
Additive Phase Jitter,
Bypass mode
n/a
t
jphPCIeG2-CC
2
Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisi
.com for latest specifications.
