1. General description
The 74LVC109A is a dual positive edge triggered JK flip-flop featuring:
• individual J and K inputs
• clock (CP) inputs
• set (SD) and reset (RD) inputs
• complementary Q and Q outputs
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input.
The J and K
inputs control the state changes of the flip-flops as described in the mode
select function table. The J and K
inputs must be stable one set-up time before the
LOW-to-HIGH clock transition for predictable operation. The JK
design allows operation
as a D-type flip-flop by tying the J and K
inputs together.
Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock
rise and fall times.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
Rev. 5 — 29 November 2012 Product data sheet
