74LVC109 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 29 November 2012 6 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
=25C.
10. Dynamic characteristics
I
CC
supply
current
V
CC
= 3.6 V; V
I
=V
CC
or GND;
I
O
=0A
-0.110-40A
I
CC
additional
supply
current
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
=V
CC
0.6 V; I
O
=0A
- 5 500 - 5000 A
C
I
input
capacitance
V
CC
= 0 V to 3.6 V;
V
I
=GNDtoV
CC
-5.0---pF
Table 6. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7
.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
nCP to nQ, nQ; see Figure 5
[2]
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 1.7 6.8 15.0 1.7 17.4 ns
V
CC
= 2.3 V to 2.7 V 2.7 3.9 8.1 2.7 9.4 ns
V
CC
= 2.7 V 1.5 3.9 7.3 1.5 9.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 3.5 6.8 1.0 8.5 ns
t
PLH
LOW to
HIGH
propagation
delay
nSD, nRD to nQ, nQ; see Figure 6
V
CC
= 1.2 V - 16 - - - ns
V
CC
= 1.65 V to 1.95 V 1.0 6.2 15.6 1.0 18.0 ns
V
CC
= 2.3 V to 2.7 V 1.5 3.6 8.3 1.5 9.7 ns
V
CC
= 2.7 V 1.5 4.5 8.2 1.5 10.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 3.3 7.0 1.0 9.0 ns
t
PHL
HIGH to
LOW
propagation
delay
nSD, nRD to nQ, nQ; see Figure 6
V
CC
= 1.2 V - 13 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 6.7 14.4 1.5 16.7 ns
V
CC
= 2.3 V to 2.7 V 2.0 3.8 7.7 2.0 9.0 ns
V
CC
= 2.7 V 1.5 4.1 7.1 1.5 9.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 3.5 6.5 1.0 8.5 ns