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74LVC109PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
74LVC109 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 29 November 2012 10 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 7. Load circuitry for switching times
Table 9. Test data
Supply voltage Input Load
V
I
t
r
, t
f
C
L
R
L
1.2 V V
CC
2 ns 30 pF 1 k
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k
2.3 V to 2.7 V V
CC
2 ns 30 pF 500
2.7V 2.7V 2.5 ns 50 pF 500
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500
74LVC109 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 29 November 2012 11 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
12. Package outline
Fig 8. Package outline SOT109-1 (SO16)
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1
99-12-27
03-02-19
076E07 MS-012
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74LVC109 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 29 November 2012 12 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
Fig 9. Package outline SOT338-1 (SSOP16)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
99-12-27
03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
8
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
max.
2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

74LVC109PW,118

Mfr. #:
Buy 74LVC109PW,118
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 3.3V DUAL JK SET
Lifecycle:
New from this manufacturer.
Delivery:
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