10
FN9039.5
December 3, 2015
the requirement, and are also readily available
standard values.
The three resistors (R
4
, R
5
, R
6
) is the recommended
approach for most cases. But if acceptable values can’t
be found, then consider 2 separate resistor dividers
(one for each pin; both from V
DD
to V
EE
). This also
allows the user to adjust or trim either trip point
independently.
Note that the top of the resistor dividers is shown in
Figure 29 as GND (Short pin). In a system where cards
are plugged into a backplane (or any other case where
pins are plugged into an edge connector) the user may
want to take advantage of the order in which pins
make contact. Typically, pins on either end of the card
make contact first (although you may not know which
end is first). If you combine that with designating a pin
near the center as the short pin GND, and make it
shorter than the rest, then it should be the last pin to
make contact.
The advantage of doing this: the V
DD
and V
EE
pin
connections are made first. The IC is powered up, but
since the top of the resistor divider is still open, both
the UV and OV pins are pulled low to V
EE
, which will
keep the gate off. This allows the IC time to get
initialized, and also allows the power supply to charge
up any input capacitance. By the time the resistor
divider makes contact, the power supply voltage on the
card is presumably stabilized, and the IC ready to
respond; when the UV pin reaches the proper voltage,
the IC will turn on the GATE of the FET, and starts the
controlled inrush current charging.
Note that this is not a requirement; if the IC gets
powered at the same time as the rest of the board, it
should be able to properly control the inrush current.
But if finer control is needed, there are many variables
involved to consider: the number of pins in the
connector; the lengths of the pins; the amount of
mechanical play in the pin-to-connector interface; the
amount of extra time versus the shorter pin length; the
amount of input capacitance versus the ability of the
power supply to charge it; the manufacturing cost
adder (if any) of different length pins; etc.
Applications: PWRGD/PWRGD
The PWRGD/PWRGD outputs are typically used to
directly enable a power module, such as a DC/DC
converter. The PWRGD (ISL6140) is used for modules
with active low enable (L version); PWRGD (ISL6150)
for those with active high enable (H version). The
modules usually have a pull-up device built-in, as well
as an internal clamp. If not, an external pull-up resistor
may be needed, since the output is open drain. If the
pin is not used, it can be left open.
For both versions, the PG comparator compares the
DRAIN pin to V
EE
(connected to the source of the FET);
if the voltage drop exceeds VPG (1.7V nominal), that
implies the drop across the FET is too high, and the
PWRGD pin should go in-active (power-NO-GOOD).
ISL6140 (L version; Figure 6): Under normal
conditions (DRAIN < VPG), the Q2 DMOS will turn on,
pulling PWRGD
low, enabling the module.
When the DRAIN is too high, the Q
2
DMOS will shut off
(high impedance), and the pin will be pulled high by
the external module (or an optional pull-up resistor or
equivalent), disabling the module. If a pull-up resistor
is used, it can be connected to any supply voltage that
doesn’t exceed the IC pin maximum ratings on the
high end, but is high enough to give acceptable logic
levels to whatever signal it is driving. An external
clamp may be used to limit the range.
The PWRGD
can also drive an opto-coupler (such as a
4N25), as shown in Figure 7 or LED (Figure 8). In both
cases, they are on (active) when power is good.
Resistors R
12
or R
13
are chosen, based on the supply
voltage, and the amount of current needed by the
loads.
+
-
+
-
V
EE
VPG (1.7V)
PWRGD
DRAIN
V
DD
+
V
IN
+
V
IN
-
ON
/OFF
V
OUT
+
V
OUT
-
C
L
Q
2
ACTIVE
ENABLE
MODULE
(SECTION OF) ISL6140
(L VERSION)
FIGURE 6. ACTIVE LOW ENABLE MODULE
LOW
OPTO
PWRGD
+
-
+
-
V
EE
VPG
PWRGD
DRAIN
V
DD
Q
2
(SECTION OF) ISL6140
(L VERSION)
FIGURE 7. ACTIVE LOW ENABLE OPTO-ISOLATOR
(1.7V)
R
12
LED (GREEN)
R
13
+
-
+
-
V
EE
VPG
PWRGD
DRAIN
V
DD
Q
2
(SECTION OF) ISL6140
(L VERSION)
FIGURE 8. ACTIVE LOW ENABLE WITH LED
(1.7V)
ISL6140, ISL6150
11
FN9039.5
December 3, 2015
ISL6150 (H version; Figure 9): Under normal
conditions (DRAIN < VPG), the Q
3
DMOS will be on,
shorting the bottom of the internal resistor to V
EE
, and
turning Q
2
off. If the pull-up current from the external
module is high enough, the voltage drop across the
6.2k resistor will look like a logic high (relative to
DRAIN). Note that the module is only referenced to
DRAIN, not V
EE
(but under normal conditions, the FET
is on, and the DRAIN and V
EE
are almost the same
voltage).
When the DRAIN voltage is high compared to VPG, Q
3
DMOS turns off, and the resistor and Q
2
clamp the
PWRGD pin to one diode drop (~0.7V) above the
DRAIN pin. This should be able to pull low against the
module pull-up current, and disable the module.
Applications: GATE Pin
To help protect the external FET, the output of the
GATE pin is internally clamped; up to an 80V supply, it
will not be any higher than 15V (nominal 14V). From
about 18V down to 10V, the GATE voltage will be
around 4V below the supply voltage; at 10V supply, the
minimum GATE voltage is 5.4V (worst case is at
-40°C).
Applications: Optional
Components
In addition to the typical application, and the variations
already mentioned, there are a few other possible
components that might be used in specific cases. See
Figure 29 for some possibilities.
If the input power supply exceeds the 100V absolute
maximum rating, even for a short transient, that could
cause permanent damage to the IC, as well as other
components on the board. If this cannot be
guaranteed, a voltage suppressor (such as the
SMAT70A, D
1
) is recommended. When placed from
V
DD
to V
EE
on the board, it will clamp the voltage.
If transients on the input power supply occur when the
supply is near either the OV or UV trip points, the GATE
could turn on or off momentarily. One possible solution
is to add a filter cap C
4
to the V
DD
pin, through
isolation resistor R
10
. A large value of R
10
is better for
the filtering, but be aware of the voltage drop across it.
For example, a 1k resistor, with 1mA of I
DD
would
have 1V across it and dissipate 1mW. Since the UV and
OV comparators are referenced with respect to the V
EE
supply, they should not be affected. But the GATE
clamp voltage could be offset by the voltage across the
extra resistor.
If there are negative transients on the DRAIN pin,
blocking diodes may help limit the amount of current
injected into the IC substrate. General purpose diodes
(such as 1N4148) may be used. Note that the ISL6140
(L version) requires one diode, while the ISL6150
(H version) requires two diodes. One consequence of
the added diodes it that the V
PG
voltage is offset by
each diode drop.
The switch SW1 is shown as a simple pushbutton. It
can be replaced by an active switch, such as an NPN or
NFET; the principle is the same; pull the UV node below
its trip point, and then release it (toggle low). To
connect an NFET, for example, the drain goes to UV;
the source to V
EE
, and the gate is the input; if it goes
high (relative to V
EE
), it turns the NFET on, and UV is
pulled low. Just make sure the NFET resistance is low
compared to the resistor divider, so that it has no
problem pulling down against it.
R
8
is a pull-up resistor for PWRGD, if there is no other
component acting as a pull-up device. The value of R8
is determined by how much current you want when
pulled low (also affected by the V
DD
voltage); and you
want to pull it low enough for a good logic low level. An
LED can also be placed in series with R
8
, if desired. In
that case, the criteria is the LED brightness versus
current.
R
7
and C
3
are used to delay the overcurrent shutdown,
as described in the OV and UV section.
Applications: “Brick”
Regulators
One of the typical loads used are DC/DC regulators,
some commonly known as “brick” regulators, (partly
due to their shape, and because it can be considered a
“building block” of a system). For a given input voltage
range, there are usually whole families of different
output voltages and current ranges. There are also
various standardized sizes and pinouts, starting with
the original “full” brick, and since getting smaller
(half-bricks and quarter-bricks are now common).
Other common features may include: all components
(except some filter capacitors) are self-contained in a
molded plastic package; external pins for connections;
and often an ENABLE input pin to turn it on or off. A hot
plug IC, such as the ISL6140, is often used to gate
power to a brick, as well as turn it on.
Many bricks have both logic polarities available (Enable
Hi or Lo input); select the ISL6140 (L version) and
ISL6150 (H version) to match. There is little difference
between them, although the L version output is usually
simpler to interface.
+
-
+
-
V
EE
VPG
PWRGD
DRAIN
VDD
+
V
IN
+
V
IN
-
ON/OFF
V
OUT
+
V
OUT
-
C
L
Q
3
Q2
RPG
6.2k
ACTIVE HIGH
ENABLE
MODULE
(SECTION OF) ISL6150
(H VERSION)
FIGURE 9. ACTIVE HIGH ENABLE MODULE
(1.7V)
ISL6140, ISL6150
12
FN9039.5
December 3, 2015
The Enable input often has a pull-up resistor or current
source, or equivalent built in; care must be taken in
the ISL6150 (H version) output that the given current
will create a high enough input voltage (remember that
current through the RPG 6.2k resistor generates the
high voltage level; (see Figure 9).
The input capacitance of the brick is chosen to match
its system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that
this input capacitance appears as the load capacitance
of the ISL6140/ISL6150.
The brick’s output capacitance is also determined by
the system, including load regulation considerations.
However, it can affect the ISL6140 and ISL6150,
depending upon how it is enabled. For example, if the
PWRGD signal is not used to enable the brick, the
following could occur. Sometime during the inrush
current time, as the main power supply starts charging
the brick input capacitors, the brick itself will start
working, and start charging its output capacitors and
load; that current has to be added to the inrush
current. In some cases, the sum could exceed the
overcurrent shutdown, which would shut down the
whole system! Therefore, whenever practical, it is
advantageous to use the PWRGD output to keep the
brick off at least until the input caps are charged up,
and then start-up the brick to charge its output caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the
input and output.
Applications: Layout
Considerations
For the minimum application, there are only 6
resistors, 2 capacitors, one IC and one FET. A sample
layout is shown in Figure 30. It assumes the IC is
8-SOIC; the FET is in a D2PAK (or similar SMD-220
package).
Although GND planes are common with multi-level
PCBs, for a -48V system, the -48V rails (both input and
output) act more like a GND than the top 0V rail
(mainly because the IC signals are mostly referenced
to the lower rail). So if separate planes for each voltage
are not an option, consider prioritizing the bottom rails
first.
Note that with the placement shown, most of the signal
lines are short, and there should not be much
interaction between them.
Although decoupling capacitors across the IC supply
pins are often recommended in general, this
application may not need one, nor even tolerate one.
For one thing, a decoupling cap would add to (or be
swamped out by) any other input capacitance; it also
needs to be charged up when power is applied. But
more importantly, there are no high speed (or any)
input signals to the IC that need to be conditioned. If
still desired, consider the isolation resistor R
10
, as
shown in Figure 29.
ISL6140, ISL6150

ISL6150IBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers 8LD HOT SWAP CNTRLR ENABLE
Lifecycle:
New from this manufacturer.
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