8
FN9039.5
December 3, 2015
be selected based on several criteria: maximum
voltage expected on the input supply (including
transients) as well as transients on the output side;
maximum current expected; power dissipation and/or
safe-operating-area considerations (due to the quick
overcurrent latch, power dissipation is usually not a
problem compared to systems where current limiting is
used; however, worst case power is usually at a level
just below the overcurrent shutdown). Other
considerations include the gate voltage threshold which
affects the r
DS(ON)
(which in turn, affects the voltage
drop across the FET during normal operation), and the
maximum gate voltage allowed (the IC clamp output is
clamped to ~14V).
R
1 -
is the overcurrent sense resistor; if the input
current is high enough, such that the voltage drop
across R
1
exceeds the SENSE comparator trip point
(50mV nominal), the GATE pin will go low, turning off
the FET, to protect the load from the excessive current.
A typical value for R1 is 0.02; this sets an overcurrent
trip point of I = V/R = 0.05/0.02 = 2.5A. So, to choose
R
1
, the user must first determine at what level of
current it should trip. Take into account worst case
variations for the trip point (50mV 10mV = 20%),
and the R
1
resistance (typically 1% or 5%). Note that
under normal conditions, there will be a voltage drop
across the resistor (V = IR), so the higher the resistor
value, the bigger the voltage drop. Also note that the
overcurrent should be set above the inrush current
level (plus the load current); otherwise, it will latch off
during that time (the alternative is to lower the in-rush
current further). One rule of thumb is to set the
overcurrent 2-3 times higher than the normal current
(see Equation 1).
CL - is the sum of all load capacitances, including the
load’s input capacitance itself. Its value is usually
determined by the needs of the load circuitry, and not
the hot plug (although there can be interaction). For
example, if the load is a regulator, then the capacitance
may be chosen based on the input requirements of
that circuit (holding regulation under current spikes or
loading, filtering noise, etc.) The value chosen will then
affect how the inrush current is controlled. Note that in
the case of a regulator, there may be capacitors on the
output of that circuit as well; these need to be added
into the capacitance calculation during inrush (unless
the regulator is delayed from operation by the PWRGD
signal, for example).
RL - is the equivalent resistive value of the load; it
determines the normal operation current delivered
through the FET. It also affects some dynamic
conditions (such as the discharge time of the load
capacitors during a power-down). A typical value might
be 48 (I = V/R = 48/48 = 1A).
R2, C1, R3, C2 - are related to the gate driver, as it
controls the inrush current.
R
2
prevents high frequency oscillations; 10 is a
typical value. R
2
= 10.
R
3
and C
2
act as a feedback network to control the
inrush current. I inrush = (Igate*C
L
)/C
2
, where C
L
is
the load capacitance (including module input
capacitance), and Igate is the gate pin charging
current, nominally 45µA. So choose a value of
acceptable inrush for the system, and then solve for
C
2
. So I = 45µA*(C
L
/C
2
). Or C
2
= (45µA*C
L
)/I.
C
1
and R
3
prevent Q
1
from turning on momentarily
when power is first applied. Without them, C
2
would
pull the gate of Q1 up to a voltage roughly equal to
VEE*C
2
/C
GS
(Q
1
) (where C
GS
is the FET gate-source
capacitance) before the ISL6140 could power up and
actively pull the gate low. Place C
1
in parallel with the
gate capacitance of Q1; isolate them from C
2
by R
3
.
C1 = (V
INMAX
- V
TH
)/V
TH
*(C
2
+C
GD
) where V
TH
is
the FET’s minimum gate threshold, Vinmax is the
maximum operating input voltage, and Cgd is the FET
gate-drain capacitance.
R3 = (V
INMAX
+ V
GATE
)/5mA its value is not
critical; a typical value is 18k.
Applications: Inrush Current
The primary function of the ISL6140 hot plug controller
is to control the inrush current. When a board is
plugged into a live backplane, the input capacitors of
the board’s power supply circuit can produce large
current transients as they charge up. This can cause
glitches on the system power supply (which can affect
other boards!), as well as possibly cause some
permanent damage to the power supply.
The key to allowing boards to be inserted into a live
backplane then is to turn on the power to the board in
a controlled manner, usually by limiting the current
allowed to flow through a FET switch, until the input
capacitors are fully charged. At that point, the FET is
fully on, for the smallest voltage drop across it.
In addition to controlling the in-rush current, the
ISL6140 also protects the board against overcurrent,
overvoltage, undervoltage, and can signal when the
output voltage is within its expected range (PWRGD).
Note that although this IC was designed for -48V
systems, it can also be used as a low-side switch for
positive 48V systems; the operation and components
are usually similar. One possible difference is the kind
of level shifting that may be needed to interface logic
signals to the UV input (to reset the latch) or PWRGD
output. For example, many of the IC functions are
referenced to the IC substrate, connected to the VEE
pin. But this pin may be considered -48V or GND,
depending upon the polarity of the system. And input
or output logic (running at 5V or 3.3V or even lower)
might be externally referenced to either VDD or VEE of
the IC, instead of GND.
R
1
VI
OC
0.05V/I
OC
typical 0.02===
(EQ. 1)
ISL6140, ISL6150
