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ISL6150IBZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
16
FN9039.5
December 3, 2015
Inrush Current
In the example in Figure 26, the supply voltage is 48V
and the load resistor (RL) is 620, for around 80mA.
The load capacitance is 100F (100V). The Sense
Resistor (R
1
) is 0.02 (trip point at 2.5A; well above
the inrush current here).
Note that the load current starts at 0 (FET off); reaches
a peak of ~850mA as the GATE voltage ramps and
turns on the FET slowly, and then settles out at 80mA,
once the CL is fully charged to the 48V. The width of
the inrush current pulse is 8ms wide. For comparison,
with the same conditions, but without the
gate-controlled FET, the current was over 20A, during a
130µs pulse.
Power Supply Ramp
Figure 27 shows the power supply voltage (to the V
DD
pin, with respect to GND at the V
EE
pin) ramping up. In
this case, the values chosen were R
4
= 562k;
R5 = 5.9k; R
6
= 13.3k; that sets the UV trip point
around 38V, and the OV trip point to 54V. Note that the
GATE starts at 0V, and stays there until the UV trip
point (38V) is exceeded; then it ramps (slowly, based
on the external components chosen) up to around 13V,
where it is clamped; it stays there until the power
supply exceeds the OV trip point at 54V (the GATE
shut-off is much faster than the turn-on). The total
time scale is 2 seconds; the V
DD
ramp speed was
simply based on the inherent characteristic of the
particular power supply used.
Overcurrent at 2.3A
In Figure 28, an Electronic Load Generator was used to
ramp the load current; no load resistor or capacitor
was connected. The sense Resistor R
1
is 0.02; that
should make the nominal overcurrent trip point 2.5A.
The GATE is high (clamped to around 13V), keeping
the FET on, as the current starts to ramp up from zero;
the GATE starts to go low (to shut off the FET) when
the load current hits 2.3A. Note that it takes only 44µs
for the GATE to shut off the FET (when the load current
equals zero).
Keep in mind that the tolerance of the sense resistor
(1% here) and the IC overcurrent trip voltage (V
CB
)
affect the accuracy of the trip point; that’s why the trip
point doesn’t necessarily equal the 2.5A design target.
PWRGD-bar
GATE
Load
Current
48V
FIGURE 26. INRUSH CURRENT
LOAD
CURRENT
48V
GATE
PWRGD-BAR
FIGURE 27. POWER SUPPLY RAMP
GATE
V
DD
OFF
ON
OFF
13V
UV = 38V
OV = 54V
V
DD
= 60V
Load Current
GATE
2.3 A
R1 = 0.02 oh
48V
No cap
FIGURE 28. OVERCURRENT AT 2.3A
LOAD CURRENT
GATE
2.3A
R1 = 0.02
48V
NO CAP
ISL6140, ISL6150
17
FN9039.5
December 3, 2015
Optional Components
D
1
is a voltage suppressor; SMAT70A or equivalent.
D
2
and D
3
are DRAIN diodes; the ISL6150 (H version)
uses both D
2
and D
3
; the ISL6140 (L version) uses
just D
2
. If neither is used, short the path of either, to
connect the DRAIN pin to C
2
and Q
1
. The 1N4148 is a
typical diode.
SW1 is a push-button switch, that can manually reset
the fault latch after an overcurrent shutdown. It can
also be replaced by a transistor switch.
R
10
and C
4
are used to filter the V
DD
voltage, such
that small transients on the input supply do not trigger
UV or OV.
R
7
and C
3
are used to delay the overcurrent shutdown.
R
7
should be shorted, if not used. See the overcurrent
section for more details.
R
8
is a pull-up resistor for PWRGD, if there is no other
component acting as a pull-up device. An LED can also
be placed in series with R
8
, if desired (see Figure 8).
C
L
is any extra output Load capacitance, which can
also be considered input capacitance for the external
module.
R
6
is used to add more hysteresis to the UV threshold,
which already has a built-in 20mV hysteresis. With R
6
,
the new thresholds with a rising and falling input are
shown in Equation 3 and 4:
Since R
6
is connected directly to the GATE output, it
will reduce the available gate current, which will reduce
the dv/dt across the MOSFET and hence the inrush
current. The value of R
6
should be kept as high as
possible (greater than 500k recommended) so that it
does not drag down the GATE voltage below the value
required to ensure the MOSFET is fully enhanced.
Figure 30 shows a sample component placement and
routing for the typical application shown in Figure 31.
ISL6140 (L)
V
DD
UV
OV
V
EE
SENSE GATE DRAIN
PWRGD
R
1
C3*
R
7
*
Q
1
C
1
R
2
R
3
C
2
D
2
*
D
3
*
R
4
D
1
*
SW1
R
8
*
CL*
C4*
GND GND
-V
IN
-V
OUT
R
10
*
R
5
R
12
GND
(SHORT PIN)
G
NFET*
(INSTEAD
OF SW1)
FIGURE 29. ISL6140/50 OPTIONAL COMPONENTS (SHOWN WITH *)
R
6
*
R
11
Vuv fallingVUVL
R5 R6 R4 R6 R4 R5++
R5 R6
------------------------------------------------------------------------------


Vgate
R4
R6
--------


–=
(EQ. 4)
ISL6140, ISL6150
18
FN9039.5
December 3, 2015
.
NOTES:
1. Layout scale is approximate; routing lines are just for
illustration purposes; they do not necessarily conform to
normal PCB design rules. High current buses are wider,
shown with parallel lines.
2. Approximate size of the above layout is 1.6 x 0.6 inches;
almost half of the area is just the FET (D2PAK or similar
SMD-220 package).
3. R
1
sense resistor is size 2512; all other R’s and C’s shown
are 0805; they can all potentially use smaller footprints, if
desired.
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the
board; all other routing can be on top level. (It’s even
possible to eliminate the via, for an all top-level route).
6. PWRGD
signal is not used here.
7. BOM (Bill Of Materials)
R
1
= 0.02 (5%)
R
2
= 10 (5%)
R
3
= 18k (5%)
R
4
= 562k (1%)
R
5
= 9.09k (1%)
R
6
= 10k (1%)
C
1
= 150nF (25V)
C
2
= 3.3nF (100V)
Q
1
= IRF530 (100V, 17A, 0.11)
G 6
D 7
V
DD
8
2 OV
3 UV
4 V
EE
1 PG
S 5
U
1
R
1
R
5
G
S
DRAIN
FET
R
4
R
3
C
2
R
2
R
6
C
1
-48V
IN
GND GND
-48V
OUT
FIGURE 30. SAMPLE LAYOUT (NOT TO SCALE)
ISL6140
V
DD
UV
OV
V
EE
SENSE GATE DRAIN
PWRGD
R
4
R
5
R
6
R
1
R
2
R
3 C
2
C
1
Q
1
CL
GND GND
-48V IN
-48V
OUT
RL
(LOAD)
FIGURE 31. TYPICAL APPLICATION
ISL6140, ISL6150
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ISL6150IBZ-T

Mfr. #:
Buy ISL6150IBZ-T
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers 8LD HOT SWAP CNTRLR ENABLE
Lifecycle:
New from this manufacturer.
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