TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 10 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
minimum JFET drain source voltage is controlled by a Direct Current (DC) feedback loop
(pin VAMCASFB) in order to limit the cascode AGC range to 10 dB. If the cascode AGC is
not required, a simple RF AGC loop is possible by using only a PIN diode. In some
conditions, noise behavior will increase. In this case pins VAMCAS and VAMCASFB have
to be left open-circuit. In FM mode, the cascode switches off the JFET bias current to
reduce the total power consumption.
The AGC detection points for AM RF AGC are at the AM mixer input (threshold
programmable via the I
2
C-bus) and the AM and FM IF AGC amplifier input (fixed
threshold).
In FM mode the AM AGC can be activated via the I
2
C-bus to sink a constant current of
1 mA from the PIN diode.
7.10 FM/AM RF AGC buffer
This output current can be used to reduce the gain of active antennas before start of
RF AGC.
The output (open-collector) sinks a current which in AM mode is proportional to the
voltage at pin TRFAMAGC and in FM mode proportional to the RF level detector voltage
(pin TFMAGC) inside the FM AGC.
8. I
2
C-bus protocol
8.1 I
2
C-bus specification
SDA and SCL HIGH and LOW levels are specified according to a 3.3 V I
2
C-bus. The bus
pins tolerate also thresholds of a 5 V bus.
The standard I
2
C-bus specification is expanded by the following definitions.
IC addresses:
1st IC address C2h: 1100001 R/W
2nd IC address C0h: 1100000 R/W
3rd IC address C4h: 1100010 R/W.
Structure of the I
2
C-bus logic: slave transceiver with auto increment.
Subaddresses are not used.
The second I
2
C-bus address can be selected by connecting pin ADDRSEL via a 120 k
resistor to ground. The third I
2
C-bus address can be selected by connecting
pin ADDRSEL via a 33 k resistor to ground.
The maximum bit rate for this device is 100 kbit/s.
The I
2
C-bus interface is extended with an enable input (pin BUSENABLE). If pin
BUSENABLE is HIGH the communication with the device is active; if pin BUSENABLE is
LOW the signals on the I
2
C-bus are ignored so that higher bit rates (> 100 kbit/s) can be
used to communicate with other devices on the same I
2
C-bus. The enable signal must not
change while bus communication takes place.
TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 11 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
No default settings at power-on reset. I
2
C-bus transmission is required to program the
IC.
8.1.1 Data transfer
Data sequence: address, byte 0, byte 1, byte 2, byte 3, byte 4 and byte 5.
The data transfer has to be in this order. The LSB of the address being logic 0 indicates a
write operation.
Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of the
byte.
The data becomes valid at the output of the internal latches with the acknowledge of each
byte. A STOP condition after any byte can shorten transmission times.
When writing to the transceiver by using the STOP condition before completion of the
whole transfer:
The remaining bytes will contain the old information
If the transfer of a byte is not completed, this byte is lost and the previous information
is available.
8.1.2 Frequency setting
For new frequency setting, in both AM and FM mode, the programmable divider is
enabled by setting bit PRESET to logic 1. To select a frequency, two I
2
C-bus
transmissions are necessary:
First: bit PRESET = 1
Second: bit PRESET = 0.
8.1.3 Restriction of the I
2
C-bus characteristic
At 40 °C the start of the acknowledge bit after transmitting the slave address exceeds the
general requirement of t
HD;DAT
< 3.45 µs. The start of acknowledge is t
ST;ACK
< 4.1 µsover
the full temperature range from 40 °Cto+85°C. This will not influence the overall
system performance, because the required set-up time t
SU;DAT
> 250 ns is fulfilled at any
condition.
8.2 I
2
C-bus protocol
8.2.1 Data transfer mode and IC address
Fig 5. Write mode
ACK-s ACK-s
DATASLAVE ADDRESS W
data transferred
(n bytes + acknowledge)
001aad050
PS
TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 12 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
[1] Pin ADDRSEL left open-circuit activates first IC address; R
ext
= 120 k at pin ADDRSEL to ground
activates second IC address; R
ext
=33k at pin ADDRSEL to ground activates third IC address.
[2] Read or write bit:
0 = write operation to TEF6721HL
1 = read operation from TEF6721HL.
8.2.2 Write mode: data byte 0
8.2.3 Write mode: data byte 1
Fig 6. Read mode
DATA
ACK-s
ACK-m
DATA
NASLAVE ADDRESS R
001aad049
PS
data transferred
(n
1 bytes + acknowledge)
Table 4: Description of I
2
C-bus format
Code Description
S START condition
Slave address W see
Table 5
Slave address R see
Table 5
ACK-s acknowledge generated by the slave
ACK-m acknowledge generated by the master
NA not acknowledge generated by the master
Data data byte
P STOP condition
Table 5: IC address byte
Address IC address
[1]
Mode
[2]
11100001R/W
21100000R/
W
31100010R/
W
Table 6: Format of data byte 0
7 6 5 4 3 2 1 0
AF PLL14 PLL13 PLL12 PLL11 PLL10 PLL9 PLL8
Table 7: Description of data byte 0 bits
Bit Symbol Description
7AFAlternative frequency. If AF = 0, then normal operation. If AF = 1, then
AF (RDS) update mode.
6 to 0 PLL[14:8] Setting of programmable counter of synthesizer PLL. Upper byte of
PLL divider word.
Table 8: Format of data byte 1
7 6 5 4 3 2 1 0
PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0

TEF6721HL/V1S,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
RF RECEIVER AM/FM/WB 64LQFP
Lifecycle:
New from this manufacturer.
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