TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 34 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
[1] Measured between pins XTAL1 and XTAL2.
[2] DAA conversion gain formula: ; where
n = 0 to 127.
[3] V
LSB
=V
DAAOUT(n+1)
V
DAAOUT(n)
[4] The AM AGC transconductance buffer delivers a sink current which is proportional to the voltage change at pin TRFAMAGC.
[5] Image rejection ratio:
V
i(max)(p)
maximum input voltage
(peak value)
1 dB compression point of
IF AGC amplifier output
voltage
V
IFAGCMSB
= 0.2 V;
V
IFAGCLSB
= 0.2 V
120 - - mV
V
IFAGCMSB
= 0.2 V;
V
IFAGCLSB
= 2.8 V
220 - - mV
V
IFAGCMSB
= 2.8 V;
V
IFAGCLSB
= 2.8 V
440 - - mV
V
IFAGCMSB
= 2.8 V;
V
IFAGCLSB
= 0.2 V
600 - - mV
Crystal frequency Digital Auto Alignment (DAA)
Output: pin VDAC
V
o(max)
maximum output voltage data byte 5 = XXX0 0000
(n=0)
7.4 - - V
V
o(min)
minimum output voltage data byte 5 = XXX1 1111
(n = 31)
- - 1.7 V
V
o(step)
DAA step accuracy n = 0 to 31 100 200 300 mV
V
o(n)
DAA output noise voltage B = 300 Hz to 22 kHz - 100 130 µV
Table 29: Dynamic characteristics
…continued
V
FMMIXOUT1
=V
AMMIXOUT1
=V
FMMIXOUT2
=V
AMMIXOUT2
=V
DDA1
=V
DDA2
=V
DDA3
=V
DDA4
=V
DDA5
= 8.5 V; V
DDA6
=5V;
V
DDD
=5V; T
amb
=25
°
C; see Figure 9; all AC values are given in RMS; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
DAAOUT
2 0.75
n
128
---------
0.125+×


× V
DAAIN
V
DAATD
+()× V
DAATD
=
V
TRFAMAGC
V
TRFAMAGC
V
TRFAMAGC
V
AMMIXIN
V
AMMIXDEC
()10 mV<
=
IRR
V
(FMMIXOUT1-FMMIXOUT2)wanted
V
(FMMIXOUT1-FMMIXOUT2)image
--------------------------------------------------------------------------------
=
TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 35 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
AFHOLD signal is used to hold the quality information for signal processing of the main channel during the alternative
frequency jumps. PLL registers are loaded during load PLL = 1, but actual frequency jumps take place at the falling edge of
this signal. IF counting is carried out during AFSAMPLE = 1. 10 µs after falling edge of AFSAMPLE result is valid for AF
and remains valid until read by microcontroller. Quality tests in IF DSP should take place during the HIGH phase of
AFSAMPLE.
t
1
is the internal TEF6721HL clock related logic delay: 100 µs.
t
2
should be > 1.1 ms to ensure correct loading of PLL for the main channel.
t
3
should be > 0 to ensure inaudible update.
t
4
= 500 µs.
Fig 7. Inaudible AF update timing diagram
t
1
AF = 1
AF channel
AF = 1
main channel
mdb415
t
2
t
3
I
2
C-bus
AFHOLD
load PLL
AFSAMPLE
audio output
of IF DSP
t
4
quality test
012
t (ms)
345678
TEF6721HL_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 20 December 2005 36 of 48
Philips Semiconductors
TEF6721HL
Car radio tuner front-end for digital IF
t
1
is the internal TEF6721HL clock related logic delay: 100 µs.
t
2
should be greater than the required PLL tuning time for the given band (FM: t
2
> 1 ms; AM: t
2
> 20 ms).
Fig 8. Preset mode timing diagram
mdb416
audio output of
IF DSP
t
1
t
2
AF = 0, PRESET = 1 AF = 0, PRESET = 0
I
2
C-bus
AFHOLD
AFSAMPLE
load PLL
quality test
0 1 n + 1
t (ms)
continuous mode
n
1
0
t
1
PLL jump

TEF6721HL/V1S,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
RF RECEIVER AM/FM/WB 64LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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