ADN2807ACPZ-RL Datasheet ADN2807ACPZ, ADN2807ACPZ-RL | P13-P15

ADN2807 Data Sheet

Rev. B | Page 12 of 21

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track the input jitter. In this case,

the VCO control voltage becomes large and saturates, and the

VCO frequency dwells at one or the other extreme of the tuning

range. The size of the VCO tuning range, therefore, has only a

small affect on the jitter accommodation. The delay-locked loop

control voltage is now larger; therefore, the phase shifter takes

on the burden of tracking the input jitter. The phase shifter range,

in UI, can be seen as a broad plateau on the jitter tolerance curve.

The phase shifter has a minimum range of 2 UI at all data rates.

The gain of the loop integrator is small for high jitter frequencies,

so larger phase differences are needed to make the loop control

voltage big enough to tune the range of the phase shifter. Large

phase errors at high jitter frequencies cannot be tolerated. In this

region, the gain of the integrator determines the jitter accom-

modation. Since the gain of the loop integrator declines linearly

with frequency, jitter accommodation is lower with higher jitter

frequency. At the highest frequencies, the loop gain is very small,

and little tuning of the phase shifter can be expected.

In this case, jitter accommodation is determined by the eye opening

of the input data, the static phase error, and the residual loop jitter

generation. The jitter accommodation is roughly 0.5 UI in this

region. The corner frequency between the declining slope and

the flat region is the closed loop bandwidth of the delay-locked

loop, which is roughly 5 MHz for OC-12 data rates and 600 kHz

for OC-3 data rates.

JITTER PEAKING

IN ORDINAR

Y PLL

ADN2807

Z(s)

X(s)

(kHz)

JITTER

GAIN

(

dB)

n psh

d psh

03877-0-014

Figure 14. Jitter Response vs. Conventional Phase-Locked Loop

Data Sheet ADN2807

Rev. B | Page 13 of 21

FUNCTIONAL DESCRIPTION

MULTIRATE CLOCK AND DATA RECOVERY

The ADN2807 recovers clock and data from serial bit streams at

OC-3, OC-12 data rates as well as the 15/14 FEC rates. The

output of the 2.5 GHz VCO is divided down in order to support

the lower data rates. The data rate is selected by the SEL[2..0]

inputs (Table 5).

Table 5. Data Rate Selection

SEL[1..0] Rate Frequency (MHz)

00 OC-12 622.08

01 OC-3 155.52

10 OC-12 FEC 666.51

11 OC-3 FEC 166.63

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN) that

are internally terminated with 50 Ω to an on-chip voltage

reference (VREF = 0.6 V typically). These inputs are normally

ac-coupled, although dc-coupling is possible as long as the

input common-mode voltage remains above 0.4 V (Figure 24 to

Figure 26 in the Applications Information section). Input offset

is factory trimmed to achieve better than 4 mV typical

sensitivity with minimal drift. The limiting amplifier can be

driven differentially or single-ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of ASE (amplified spontaneous emission) noise by

applying a differential voltage input of ±0.8 V to SLICEP/N

inputs. If no adjustment of the slice level is needed, SLICEP/N

must be tied to VCC.

LOSS-OF-SIGNAL (LOS) DETECTOR

The receiver front end level signal detect circuit indicates when

the input signal level has fallen below a user adjustable threshold.

The threshold is set with a single external resistor from THRADJ

(Pin 1) to GND. The LOS comparator trip point versus the

resistor value is illustrated in Figure 4 (this is only valid for

SLICEP = SLICEN = VCC). If the input level to the ADN2807

drops below the programmed LOS threshold, SDOUT (Pin 45)

will indicate the loss-of-signal condition with a Logic 1. The

LOS response time is ~300 ns by design but will be dominated

by the RC time constant in ac-coupled applications. If the LOS

detector is used, the quantizer slice adjust pins must both be tied to

VCC. This is to avoid interaction with the LOS threshold level.

Note that it is not expected to use both LOS and slice adjust at

the same time. Systems with optical amplifiers need the slice

adjust to evade ASE. However, a loss-of-signal in an optical link

that uses optical amplifiers causes the optical amplifier output

to be full-scale noise. Under this condition, the LOS would not

detect the failure. In this case, the loss-of-lock signal indicates

the failure because the CDR circuitry is unable to lock onto a

signal that is full-scale noise.

REFERENCE CLOCK

There are three options for providing the reference frequency to

the ADN2807: differential clock, single-ended clock, or crystal

oscillator. See Figure 15 to Figure 17 for example

configurations.

100k

Ω 100kΩ

FFER

ADN2807

VCC/2

REFCLK

REFCLKP

CRYSTAL

OSCILLATOR

VCC

REFSEL

03877-0-015

Figure 15. Differential REFCLK Configuration

OUT

100kΩ 100kΩ

FFER

ADN2807

VCC/2

REFCLKN

REFCLKP

YSTAL

OSCILLATO

XO2

VCC

REFSEL

CLK

OSC

VCC

03877-0-016

Figure 16. Single-Ended REFCLK Configuration

ADN2807 Data Sheet

Rev. B | Page 14 of 21

100kΩ 100kΩ

BUFFER

ADN2807

VCC/2

REFCLKN

REFCLKP

CRYSTAL

OSCILLATOR

XO1

XO2

REFSEL

19.44MHz

VCC

03877-0-017

Figure 17. Crystal Oscillator Configuration

The ADN2807 can accept any of the following reference clock

frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/

LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/

LVDS levels via the REFCLKN/P inputs, independent of data

rate. The input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV

(e.g., LVPECL or LVDS) or a standard single-ended low voltage

TTL input, providing maximum system flexibility. The

appropriate division ratio can be selected using the REFSEL0/1

pins according to Table 6. Phase noise and duty cycle of the

reference clock are not critical, and 100 ppm accuracy is

sufficient.

An on-chip oscillator to be used with an external crystal is also

provided as an alternative to using the REFCLKN/P inputs.

Details of the recommended crystal are given in Table 7.

Table 6. Reference Frequency Selection

REFSEL REFSEL[1..0] Applied Reference Frequency (MHz)

1 00 19.44

1 01 38.88

1 10 77.76

1 11 155.52

0 XX REFCLKP/N Inactive. Use 19.44 MHz

XTAL on Pins XO1, XO2 (Pull REFCLKP

to VCC)

Table 7. Required Crystal Specifications

Parameter Value

Mode Series Resonant

Frequency/Overall Stability 19.44 MHz ± 100 ppm

Frequency Accuracy ±100 ppm

Temperature Stability ±100 ppm

Aging ±100 ppm

ESR 50 Ω max

REFSEL must be tied to VCC when the REFCLKN/P inputs are

active or to VEE when the oscillator is used. No connection

between the XO pin and REFCLK input is necessary (Figure 15

to Figure 17). Note that the crystal must operate in series resonant

mode, which renders it insensitive to external parasitics. No

trimming capacitors are required.

LOCK DETECTOR OPERATION

The lock detector monitors the frequency difference between

the VCO and the reference clock and deasserts the loss-of-lock

signal when the VCO is within 500 ppm of center frequency.

This enables the phase loop, which then maintains phase lock,

unless the frequency error exceeds 0.1%. If this occurs, the loss-

of-lock signal is reasserted and control returns to the frequency

loop, which will reacquire and maintain a stable clock signal at

the output. The frequency loop requires a single external

capacitor between CF1 and CF2. The capacitor specification is

given in Table 8.

Table 8. Recommended C

Capacitor Specification

Parameter Value

Temperature Range –40°C to +85°C

Capacitance >3.0 µF

Leakage <80 nA

Rating >6.3 V

1000 500 0 500

1000 f

VCO

ERROR

(ppm)

LOL

03877-0-018

Figure 18. Transfer Function of LOL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

ADN2807ACPZ-RL

Mfr. #:

Buy ADN2807ACPZ-RL

Manufacturer:

Description:

Timers & Support Products 155/622Mbps CDR w/ PA Low Power I.C

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADN2807ACPZ-RL

ADN2807ACPZ-RL

Products related to this Datasheet