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ADN2807ACPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ADN2807 Data Sheet
Rev. B | Page 6 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03877-002
THRADJ
VCC
VEE
VREF
PIN
NIN
SLICEP
SLICEN
VEE
LOL
XO1
XO2
REFCLKN 13
REFCLKP 14
REFSEL 15
VEE 16
TDINP 17
TDINN 18
VEE 19
VCC 20
CF1 21
VEE 22
REFSEL1 23
REFSEL0 24
VCC
NOTES
1. EXPOSED PAD IS TIED OFF TO VCC PLANE WITH VIAS.
VCC
VEE
VEE
SEL0
NC
SEL1
VEE
VCC
VEE
VCC
CF2
LOOPEN
VCC
VEE
SDOUT
BY
PASS
VEE
VEE
CLKOUTP
CLKOUTN
SQUELCH
DATAOUTP
DATAOUTN
1
2
3
4
5
6
7
44
45
46
47
48
43
42
41
40
39
38
37
ADN2807
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
PIN 1
INDICATOR
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
1
THRADJ
AI
LOS Threshold Setting Resistor.
2, 26, 28 VCC P Analog Supply.
3, 9, 16, 19,
22, 27, 29, 33,
34, 42, 43, 46
VEE
P
Ground.
4
VREF
AO
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
5 PIN AI Differential Data Input.
6
NIN
AI
Differential Data Input.
7
SLICEP
AI
Differential Slice Level Adjust Input.
8
SLICEN
AI
Differential Slice Level Adjust Input.
10
LOL
DO
Loss-of-Lock Indicator. LVTTL active high.
11
XO1
AO
Crystal Oscillator.
12
XO2
AO
Crystal Oscillator.
13
REFCLKN
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
14
REFCLKP
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
15
REFSEL
DI
Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL.
17
TDINP
AI
Differential Test Data Input. CML.
18
TDINN
AI
Differential Test Data Input. CML.
20, 47
VCC
P
Digital Supply.
21 CF1 AO Frequency Loop Capacitor.
23
REFSEL1
DI
Reference Frequency Select (See Table 6) LVTTL.
24
REFSEL0
DI
Reference Frequency Select (See Table 6) LVTTL.
25
CF2
AO
Frequency Loop Capacitor.
30
SEL1
DI
Data Rate Select (See Table 5) LVTTL.
31
NC
No Connect.
32
SEL0
DI
Data Rate Select (See Table 5) LVTTL.
35, 36
VCC
P
Output Driver Supply.
37
DATAOUTN
DO
Differential Retimed Data Output. CML.
38
DATAOUTP
DO
Differential Retimed Data Output. CML.
39
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
40
CLKOUTN
DO
Differential Recovered Clock Output. CML.
41
CLKOUTP
DO
Differential Recovered Clock Output. CML.
44
BYPASS
DI
Bypass CDR Mode. Active high. LVTTL.
45
SDOUT
DO
Loss-of-Signal Detect Output. Active high. LVTTL.
48
LOOPEN
DI
Enable Test Data Inputs. Active high. LVTTL.
Not applicable EPAD FP
Exposed Pad. Exposed pad is tied off to VCC plane with vias.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, FP = floating pad.
Data Sheet ADN2807
Rev. B | Page 7 of 21
T
S
T
H
CLKOUTP
DATAOUTP/N
03877-0-003
Figure 3. Output Timing
RESISTANCE (kΩ)
0 100
18
16
0
mV
8
6
4
2
12
10
14
THRADJ RESISTOR VS. LOSTRIP POINT
10 20 30 40 50 60 70 80 90
03877-0-004
Figure 4. LOS Comparator Trip Point Programming
0 101 2 3 4 5 6 7 8 9
03877-0-005
HYSTERESIS (dB)
10
9
0
FREQUENCY
5
4
3
2
7
6
8
1
Figure 5. LOS Hysteresis OC-3, −40°C, 3.6 V,
2
23
–1 PRBS Input Pattern, R
TH
= 90 kΩ
ADN2807 Data Sheet
Rev. B | Page 8 of 21
HYSTERESIS (dB)
18
16
0
FREQUENCY
8
6
4
2
12
10
14
03877-0-006
0 10
1 2 3 4
5
6
7
8
9
Figure 6. LOS Hysteresis OC-12, −40°C, 3.6 V,
2
23
–1 PRBS Input Pattern, R
TH
= 90 kΩ
OUTP
OUTN
V
SE
V
CML
0V
OUTP–OUTN
V
SE
V
DIFF
03877-0-007
Figure 7. Single-Ended vs. Differential Output Specifications
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ADN2807ACPZ-RL

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Timers & Support Products 155/622Mbps CDR w/ PA Low Power I.C
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