KAF−16200
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region are light shielded pixels that include 36 leading dark
pixels on every line. There are also 30 full dark lines at the
start and 23 full dark lines at the end of every frame. Under
normal circumstances, these pixels do not respond to light
and may be used as a dark reference.
Dummy Pixels
Within each horizontal shift register there are 20 leading
additional shift phases 1 + 10 + 4 + 1 + 4 (See Figure 2).
These pixels are designated as dummy pixels and should not
be used to determine a dark reference level.
Active Buffer Pixels
Forming the outer boundary of the effective active pixel
region, there are 20 unshielded active buffer pixels between
the photoactive area and the dark reference. These pixels are
light sensitive but they are not tested for defects and
non−uniformities. For the leading 20 active column pixels,
the first 4 pixels are covered with blue pigment while the
remaining are arranged in a Bayer pattern (R, GR, GB, B).
CTE Monitor Pixels
Two CTE test columns, one on each of the leading and
trailing ends and one CTE test row are included for
manufacturing test purposes.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the device. These
photon−induced electrons are collected locally by the
formation of potential wells at each photogate or pixel site.
The number of electrons collected is linearly dependent on
light level and exposure time and non−linearly dependent on
wavelength. When the pixel’s capacity is reached, excess
electrons are discharged into the lateral overflow drain to
prevent crosstalk or ‘blooming’. During the integration
period, the V1 and V2 register clocks are held at a constant
(low) level.
Charge Transport
The integrated charge from each photogate (pixel) is
transported to the output using a two−step process. Each line
(row) of charge is first transported from the vertical CCDs
to a horizontal CCD register using the V1 and V2 register
clocks. The horizontal CCD is presented with a new line on
the falling edge of V2 while H1 is held high. The horizontal
CCDs then transport each line, pixel by pixel, to the output
structure by alternately clocking the H1 and H2 pins in a
complementary fashion. A separate connection to the last
H1 phase (H1L) is provided to improve the transfer speed of
charge to the floating diffusion output amplifier. On each
falling edge of H1L a new charge packet is dumped onto a
floating diffusion and sensed by the output amplifier.
