©2012 Integrated Device Technology, Inc.
1
JUNE 2012
DSC-5670/9
Functional Block Diagram
◆◆
◆◆
◆
Full hardware support of semaphore signaling between
ports on-chip
◆◆
◆◆
◆
Fully asynchronous operation from either port
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆◆
◆◆
◆
Sleep Mode Inputs on both ports
◆◆
◆◆
◆
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
◆◆
◆◆
◆
Single 2.5V (±100mV) power supply for core
◆◆
◆◆
◆
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆◆
◆◆
◆
Available in a 256-ball Ball Grid Array and 208-ball fine pitch
Ball Grid Array
◆◆
◆◆
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆
Green parts available, see ordering information
Features
◆◆
◆◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆◆
◆◆
◆
RapidWrite Mode simplifies high-speed consecutive write
cycles
◆◆
◆◆
◆
Dual chip enables allow for depth expansion without
external logic
◆◆
◆◆
◆
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
◆◆
◆◆
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆
Busy and Interrupt Flags
◆◆
◆◆
◆
On-chip port arbitration logic
HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
IDT70T633/1S
1. Address A18x is a NC for IDT70T631.
2. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master (M/S=VIH).
3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
CE
0R
R/
W
R
CE
1R
LB
R
UB
R
512/256K x 18
MEMORY
ARRAY
Address
Decoder
A
18R
(1)
A
0R
Address
Decoder
CE
0L
R/
W
L
CE
1L
LB
L
UB
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
I/O
0L
-I/O
17L
I/O
0R
-I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
CE
0R
CE
1R
5670 drw 01
A
18L
(1)
A
0L
ZZ
CONTROL
LOGIC
ZZ
L
(4)
ZZ
R
(4)
JTAG
TCK
TRST
TMS
TDI
TDO
INT
L
(3)
SEM
L
BUSY
L
(2,3)
BUSY
R
(2,3)
SEM
R
IN T
R
(3)
NOTES: