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70T631S12BCI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configurations
(1,2,3)
(con't.)
NOTES:
1. All V
DD pins must be connected to 2.5V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to V
SS (0V).
3. All V
SS pins must be connected to ground.
4. A
18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
1716
15
1412 13
10
9876543
21
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
NC V
SS
A
4L
INT
L
SEM
L
NCA
8L
A
12L
A
16L
V
SS
NC
OPT
L
A
0L
NC V
SS
NC
NC
A
1L
A
5L
BUSY
L
V
SS
CE
0L
CE
1L
NC
A
9L
A
13L
A
17L
I/O
8L
V
DDQR
V
SS
V
DD QL
I/O
9R
V
DDQR
V
DD
A
2L
A
6
L
R/
W
L
V
SS
UB
L
A
10L
A
14 L
A
18L
(4)
NC
I/O
8R
V
DD
I/O
11L
V
SS
I/O
10L
NC V
DD
A
3L
NC
OE
L
NC
I/O
11R
V
DDQR
I/O
10 R
V
DDQL
NC
NC
V
SS
NC
V
SS
I/O
12L
NC
V
DD
NC V
DDQR
I/O
12R
V
DD QL
V
DD
V
SS
ZZ
R
NC I/O
14L
V
DDQR
V
DD QL
NC
I/O
15R
V
SS
I/O
7R
V
DDQL
I/O
7L
A
15L
A
11L
A
7L
LB
L
I/O
6L
NC
V
SS
NC
V
SS
I/O
6R
NC
NC V
DDQL
I/O
5L
NC
V
DD
NC
V
SS
I/O
5R
ZZ
L
V
DDQR
I/O
3R
V
DDQL
I/O
4R
V
SS
I/O
4L
V
SS
I/O
3L
NC
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
1R
NC
V
SS
NC I/O
15 L
A
16R
A
12R
A
8R
NC
V
DD
SEM
R
INT
R
V
DDQR
NC I/O
1L
NC
V
SS
NC I/O
17R
A
17R
A
13R
A
9R
NC
CE
0R
CE
1R
V
DD
V
SS
BUSY
R
V
SS
V
DD
V
SS
V
DDQL
I/O
0R
V
DD QR
NC I/O
17L
V
DDQL
NC
A
18R
(4)
A
14R
A
10R
UB
R
V
SS
NC
NCV
SS
I/O
2R
NC
V
SS
NC
V
DD
A
15R
A
11R
A
7R
LB
R
OE
R
M/
S
R/
W
R
V
DDQL
I/O
2L
OPT
R
NC I/O
0L
70T633/1BF
BF-208
(5,6)
208-Ball BGA
Top View
(7)
5670 drw 02b
I/O
13L
I/O
14R
V
SS
I/O
13R
V
SS
I/O
16R
I/O
16L
V
DDQR
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
NC
V
DDQR
V
SS
V
DD
V
SS
NC
V
DD
V
DD
TDO
TDI
TCK
TMS
TR ST
V
SS
03/12/03
5
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port Right Port Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables (Input)
R/W
L
R/W
R
Read/Write Enable (Input)
OE
L
OE
R
Output Enable (Input)
A
0L
- A
18L
(1)
A
0R
- A
18R
(1)
Address (Input)
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable (Input)
INT
L
INT
R
Interrupt Flag (Output)
BUSY
L
BUSY
R
Busy Flag (Output)
UB
L
UB
R
Upper Byte Select (Input)
LB
L
LB
R
Lower Byte Select (Input)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(2)
(Input)
OPT
L
OPT
R
Option for selecting V
DDQX
(2,3)
(Input)
ZZ
L
ZZ
R
Sleep Mode Pin
(4)
(Input)
M/S Master or Slave Select (Input)
(5)
V
DD
Power (2.5V)
(2)
(Input)
V
SS
Ground (0V) (Input)
TDI Test Data Input
TDO Test Data Output
TCK Test Logic Clock (10MHz) (Input)
TMS Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
5670 tbl 01
NOTES:
1. Address A
18x is a NC for IDT70T631.
2. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/O
X.
3. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master
(M/S=V
IH).
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
NOTE:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
Truth Table I—Read/Write and Enable Control
(1)
OE SEM CE
0
CE
1
UB LB
R/W ZZ
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X H H X X X X L High-Z High-Z Deselected–Power Down
X H X L X X X L High-Z High-Z Deselected–Power Down
X H L H H H X L High-Z High-Z Both Bytes Deselected
XHLHHLLLHigh-Z D
IN
Write to Lower Byte
XHLHLHLL D
IN
High-Z Write to Upper Byte
XHLHLLLL D
IN
D
IN
Write to Both Bytes
LHLHHLHLHigh-ZD
OUT
Read Lower Byte
LHLHLHHLD
OUT
High-Z Read Up pe r Byte
LHLHLLHL D
OUT
D
OUT
Read Both Bytes
H H L H L L X L High-Z High-Z Outputs Disabled
X X X X X X X H High-Z High-Z High-Z Sleep Mode
5670 tbl 02
Truth Table II – Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to I/O
0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE
0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = V
IL.
Inputs
(1)
Outputs
Mode
CE
(2)
R/W
OE UB LB SEM
I/O
1-17
I/O
0
HHL L L LDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
(3)
H
↑
XXL L X DATA
IN
Write I/O
0
into Semaphore Flag
LXXXX L
______ ______
Not Allowe d
5670 tbl 03
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

70T631S12BCI

Mfr. #:
Buy 70T631S12BCI
Manufacturer:
IDT
Description:
SRAM 256K X 18 STD-PWR 2.5V DUAL PORT RAM
Lifecycle:
New from this manufacturer.
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