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IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
RapidWrite Mode Write Cycle
Unlike other vendors' Asynchronous Random Access Memories,
the IDT70T633/1 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
During this new RapidWrite Mode, the end of the write cycle is now
defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles.
Care must be taken to still meet the Write Cycle time (t
WC), the time in
which the Address inputs must be stable. Input data setup and hold times
(t
DW and tDH) will now be referenced to the ending address transition. In
this RapidWrite Mode the I/O will remain in the Input mode for the duration
of the operations due to R/W being held low. All standard Write Cycle
specifications must be adhered to. However, tAS and tWR are only
applicable when switching between read and write operations. Also,
there are two additional conditions on the Address Inputs that must also
be met to ensure correct address controlled writes. These specifications,
the Allowable Address Skew (t
AAS) and the Address Rise/Fall time (tARF),
must be met to use the RapidWrite Mode. If these conditions are not met
there is the potential for inadvertent write operations at random intermediate
locations as the device transitions between the desired write addresses.
5670 drw 08
t
WC
t
WC
t
WC
t
EW
t
WP
t
WZ
t
DH
t
DW
t
DW
t
DW
t
OW
t
WR
ADDRESS
CE or SEM
(6)
BEn
R/W
DATA
IN
DATA
OUT
(2)
(5)
(5)
t
DH
t
DH
(4)
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle
(1,3)
NOTES:
1. OE = V
IL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (t
EW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
