DS4026S+YCN Datasheet DS4026S+ECN, DS4026S+JCC, DS4026S+YCN | P10-P12

DS4026

10MHz to 51.84MHz TCXO

10 ______________________________________________________________________________________

Read Mode

In the temperature register (see the

Temperature

table), temperature is represented

as a 12-bit code and is accessible at location 02h and

03h. The upper 8 bits are at location 02h and the lower

4 bits are in the upper nibble of the byte at location

03h. Upon power reset, the registers are set to a +25°C

default temperature and the controller starts a tempera-

ture conversion. The temperature register stores new

temperature readings.

The current temperature is loaded into the (user) tem-

perature registers when a valid I

C slave address and

write is received and when a word address is received.

Consequently, if the two temperature registers are read

in individual I

C transactions, it is possible for a tem-

perature conversion to occur between reads, and the

results can be inaccurate. To prevent this from occur-

ring, the registers should be read using a single, multi-

byte read operation (Figure 5). I

C reads do not affect

the internal temperature registers.

C Serial Data Bus

The DS4026 supports a bidirectional I

C bus and data

transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiv-

ing data is defined as a receiver. The device that con-

trols the message is called a master. The devices that

are controlled by the master are slaves. The bus must

be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions. The DS4026

operates as a slave on the I

C bus. Connections to the

bus are made through the open-drain I/O lines SDA

and SCL. Within the bus specifications, a standard

mode (100kHz maximum clock rate) and a fast mode

(400kHz maximum clock rate) are defined. The DS4026

works in both modes.

The following bus protocol has been defined (Figure 3):

• Data transfer can be initiated only when the bus is

not busy.

Table 1. Register Map

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION

00 DCOMP SIGN FTUNEH Frequency Tuning High

01 FTUNEL Frequency Tuning Low

02 SIGN TREGH Temperature MSB

03 TREGL Temperature LSB

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12 678 9 12 893–7

Figure 3. I

C Data Transfer Overview

DS4026

10MHz to 51.84MHz TCXO

______________________________________________________________________________________ 11

• During data transfer, the data line must remain stable

whenever the clock line is high. Changes in the data

line while the clock line is high are interpreted as

control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

high.

START data transfer: A change in the state of the

data line from high to low, while the clock line is high,

defines a START condition.

STOP data transfer: A change in the state of the

data line from low to high, while the clock line is high,

defines a STOP condition.

Data valid: The state of the data line represents valid

data when, after a START condition, the data line is

stable for the duration of the high period of the clock

signal. The data on the line must be changed during

the low period of the clock signal. There is one clock

pulse per bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number

of data bytes transferred between the START and the

STOP conditions is not limited, and is determined by

the master device. The information is transferred

byte-wise and each receiver acknowledges with a

ninth bit.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowledge

(ACK) after the reception of each byte. The master

device must generate an extra clock pulse that is

associated with this acknowledge bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave. In

this case, the slave must leave the data line high to

enable the master to generate the STOP condition.

Figures 4 and 5 detail how data transfer is accom-

plished on the I

C bus. Depending upon the state of

the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master is

the slave address. Next follows a number of data

bytes. The slave returns an acknowledge (ACK) bit

after each received byte.

Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is trans-

mitted by the master. The slave then returns an

acknowledge bit. Next follows a number of data

bytes transmitted by the slave to the master. The

master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last

received byte, a not acknowledge (NACK) is

returned.

The master device generates all the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a repeat-

ed START condition. Because a repeated START

condition is also the beginning of the next serial

transfer, the bus is not released.

AXXXXXXXXA1000001S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S = START

A = ACKNOWLEDGE

P = STOP

R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h

<R/W>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

<WORD

ADDRESS (n)>

Figure 4. Slave Receiver Mode (Write Mode)

AXXXXXXXXA1000001S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S = START

A = ACKNOWLEDGE

P = STOP

A = NOT ACKNOWLEDGE

R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h

<R/W>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE IS FOLLOWED BY

A NOT ACKNOWLEDGE (A) SIGNAL

Figure 5. Slave Transmitter Mode (Read Mode)

DS4026

10MHz to 51.84MHz TCXO

12 ______________________________________________________________________________________

The DS4026 can operate in the following two modes:

Slave receiver mode (write mode): Serial data and

clock are received through SDA and SCL. After each

byte is received, an acknowledge bit is transmitted.

START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address

recognition is performed by hardware after reception

of the slave address and direction bit. The slave

address byte is the first byte received after the mas-

ter generates a START condition. The slave address

byte contains the 7-bit DS4026 address, which is

1000001, followed by the direction bit (R/W), which is

0 for a write. After receiving and decoding the slave

address byte, the DS4026 outputs an acknowledge

on SDA. After the DS4026 acknowledges the slave

address and write bit, the master transmits a word

address to the DS4026. This sets the register pointer

on the DS4026, with the DS4026 acknowledging the

transfer. The master can then transmit zero or more

bytes of data, with the DS4026 acknowledging each

byte received. The register pointer increments after

each data byte is transferred. The master generates

a STOP condition to terminate the data write.

Slave transmitter mode (read mode): The first byte

is received and handled as in the slave receiver

mode. However, in this mode, the direction bit indi-

cates that the transfer direction is reversed. Serial

data is transmitted on SDA by the DS4026 while the

serial clock is input on SCL. START and STOP condi-

tions are recognized as the beginning and end of a

serial transfer. Address recognition is performed by

hardware after reception of the slave address and

direction bit. The slave address byte is the first byte

received after the master generates a START condi-

tion. The slave address byte contains the 7-bit

DS4026 address, which is 1000001, followed by the

direction bit (R/W), which is 1 for a read. After receiv-

ing and decoding the slave address byte, the

DS4026 outputs an acknowledge on SDA. The

DS4026 then begins to transmit data starting with the

the register pointer is not written to before the initia-

tion of a read mode, the first address that is read is

the last one stored in the register pointer. The

DS4026 must receive a not acknowledge to end a

read.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

DS4026S+YCN

Mfr. #:

Buy DS4026S+YCN

Manufacturer:

Maxim Integrated

Description:

TCXO Oscillators 19.6608MHz TCXO

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DS4026S+YCN

DS4026S+YCN

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