DS4026
Note 1: Typical values are at +25°C, nominal supply voltages, unless otherwise indicated.
Note 2: Voltages referenced to ground.
Note 3: Limits at -40°C are guaranteed by design and not production tested.
Note 4: Specified with I
2
C bus inactive.
Note 5: Guaranteed by design and not production tested.
Note 6: Frequency stability vs. temperature is defined as (Δf
MAX
- Δf
MIN
)/2.
Note 7: Maximum power-supply variations to meet the specification are 5%.
Note 8: Crystal vendor specification.
Note 9: Holdover is defined as (f
MAX
- f
MIN
)/2 as measured within a 24-hour period. Warmup time = 1 hour.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
need only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement that t
SU:DAT
≥ 250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does not
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 =
1250ns before the SCL line is released.
Note 14: C
B
—total capacitance of one bus line in pF.
AC ELECTRICAL CHARACTERISTICS—I
2
C SERIAL INTERFACE (continued)
(V
CC
= 3.135V to 3.465V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
