DS4026
10MHz to 51.84MHz TCXO
_______________________________________________________________________________________ 7
GNDA
0.1μF
0.1μF
0.1μF
20Ω
V
REF
100μF ±20%
CERAMIC
3.3V
3.3V
3.3V ±5%
V
CC
V
OSC
GNDOSC
N.C.
N.C.
N.C.
V
CCD
FOUT
GNDD
SCL
SDA
GND
N.C.
N.C.
DS4026
Pin Description
PIN NAME FUNCTION
1 GNDA Ground for DAC
2 V
REF
Voltage Reference Output. This pin must be decoupled with a 100μF ceramic capacitor to ground.
3 V
CC
Power Supply for Digital Control and Temperature Sensor. This pin must be decoupled with a
100nF capacitor to ground.
4 V
OSC
Power Supply for Oscillator Circuit. This pin must be decoupled with a 0.1μF capacitor to ground.
5 GNDOSC Ground for Oscillator Circuit
6–10 N.C. No Connection. Must be connected to ground.
11 GND Ground for Digital Control, Temperature Sensor, and Controller Substrate
12 SDA
Serial Data Input/Output. SDA is the data input/output for the I
2
C interface. This open-drain pin
requires an external pullup resistor.
13 SCL
Serial Clock Input. SCL is the clock input for the I
2
C Interface and is used to synchronize data
movement on the serial interface.
14 GNDD Ground for Oscillator Output Driver
15 FOUT Frequency Output, CMOS Push-Pull
16 V
CCD
Power Supply for Oscillator Output Driver. This pin must be decoupled with a 0.1μF capacitor to
ground. A 20 resistor must be placed in series between the power supply and V
CCD
.
Figure 1. Typical Operating Circuit
DS4026
10MHz to 51.84MHz TCXO
8 _______________________________________________________________________________________
TEMP
SENSOR
V
CC
V
CC
GND
V
OSC
GNDOSC GNDD
V
REF
V
CCD
FOUT
GNDA
SCL
SDA
I
2
C
INTERFACE
CONTROLLER
DAC
CMOS
BUFFER
A/D
GND
EEPROM
ARRAY
GND
GND
V
CC
V
CC
DS4026
Figure 2. Functional Diagram
Detailed Description
The DS4026 is a TCXO capable of operating at 3.3V
±5%, and it allows digital tuning of the fundamental fre-
quency. The device is calibrated in the factory to
achieve an accuracy of ±1ppm over the industrial tem-
perature range, and its minimum pullability is ±8ppm
with a typical resolution of 1ppb (typ) per LSB.
The DS4026 contains the following blocks:
Oscillator block with variable capacitor for compen-
sation
Output driver block
Temperature sensor
Controller to read the temperature, control lookup
table, and adjust the DAC input
DAC output to adjust the capacitive load
•I
2
C interface to communicate with the chip
The oscillator block consists of an amplifier and variable
capacitor in a Pierce crystal oscillator with a crystal res-
onator of fundamental mode. The oscillator amplifier is a
single transistor amplifier and its transconductance is
temperature compensated. The variable capacitor is
adjusted by the DAC to provide temperature compensa-
tion. With the FTUNEH and FTUNEL registers, a minimum
pullability of ±8ppm (±5ppm for 10MHz) is achieved with
a typical resolution of 1ppb (typ) per LSB.
DS4026
10MHz to 51.84MHz TCXO
_______________________________________________________________________________________ 9
The output driver is a CMOS square-wave output with
symmetrical rise and fall time.
The temperature sensor provides a 12-bit temperature
reading with a resolution of 0.0625°C. The sensor is in
continuous conversion mode. If DCOMP is set, conver-
sions continue but temperature updates are inhibited.
The controller coordinates the conversion of tempera-
ture into digital codes. When the temperature reading is
different from the previous one or the frequency tuning
register is changed, the controller looks up the two cor-
responding capacitance trim codes from the lookup
table at a 0.5°C increment. The trim codes are interpo-
lated to 0.0625°C resolution.
The result is added with the tuning value from the fre-
quency tuning register and loaded into the DAC regis-
ters to adjust voltage output. The monotonic DAC
provides an analog voltage based on temperature
compensation to drive the variable capacitor.
The DS4026 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identification code fol-
lowed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed.
Address Map
Disable Compensation Update (DCOMP)
DCOMP is bit 7 of the frequency tuning register (see
the
Frequency Tuning Register (00h–01h), POR = 00h
table). When set to logic 1, this bit’s temperature-com-
pensation function is disabled. This disabling prevents
the variable capacitor in the oscillator block from
changing. However, the temperature register still per-
forms temperature conversions. The temperature trim
code from the last temperature conversion before
DCOMP is enabled is used for temperature compensa-
tion. The FTUNE registers are still functional when
DCOMP is disabled.
The frequency tuning registers adjust the base frequen-
cy. The frequency tuning value is represented in two’s
complement data. Bit 6 of FTUNEH is the sign, bit 5 is
the MSB, and bit 0 of FTUNEL is the LSB (see Table 1).
When the tuning register low (01h) is programmed with
a value, the next temperature update cycle sums the
programmed value with the factory compensated
value. This allows the user to digitally control the base
frequency using the I
2
C protocol.
These frequency tuning register bits allow the tuning of
the base frequency. Each bit typically represents
about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL =
FFh, the device pushes the base frequency by approx-
imately +15ppm.
Frequency Tuning Register (00h–01h), POR = 00h
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h DCOMP Sign Data Data Data Data Data Data
POR 0 0 0 0 0 0 0 0
01h Data Data Data Data Data Data Data Data
POR 0 0 0 0 0 0 0 0
Temperature Register (02h–03h)
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
02h Sign Data Data Data Data Data Data Data
POR 0 0 0 0 0 0 0 0
03h Data Data Data Data 0 0 0 0
POR 0 0 0 0 0 0 0 0

DS4026S+YCN

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
TCXO Oscillators 19.6608MHz TCXO
Lifecycle:
New from this manufacturer.
Delivery:
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