General Description
The DS28E36 is a DeepCover
®
secure authenticator
that provides a core set of cryptographic tools derived
from integrated asymmetric (ECC-P256) and symmetric
(SHA-256) security functions. In addition to the security
services provided by the hardware implemented crypto
engines, the device integrates a FIPS/NIST true random
number generator (RNG), 8Kb of secured EEPROM, a
decrement-only counter, two pins of configurable GPIO,
and a unique 64-bit ROM identification number (ROM
ID). This unique ROM ID is used as a fundamental input
parameter for cryptographic operations and also serves
as an electronic serial number within the application. The
DS28E36 communicates over the single-contact 1-Wire
®
bus at overdrive speed. The communication follows the
1-Wire protocol with the ROM ID acting as node address
in the case of a multidevice 1-Wire network.
The ECC public/private key capabilities operate from
the NIST defined P-256 curve and include FIPS 186
compliant ECDSA signature generation and verification
to support a bidirectional asymmetric key authentication
model. The SHA-256 secret-key capabilities are compli-
ant with FIPS 180 and are flexibly used either in conjunc-
tion with ECDSA operations or independently for multiple
HMAC functions.
Two GPIO pins can be independently operated under
command control and include configurability supporting
authenticated and nonauthenticated operation including
an ECDSA-based crypto-robust mode to support secure-
boot of a host processor.
DeepCover embedded security solutions cloak sensitive
data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
Applications
IoT Node Crypto-Protection
Accessory and Peripheral Secure Authentication
Secure Storage of Cryptographic Keys for a Host
Controller
Secure Boot or Download of Firmware and/or System
Parameters
Benets and Features
ECC-256 Compute Engine
FIPS 186 ECDSA P256 Signature and Verication
ECDH Key Exchange with Authentication Prevents
Man-in-the-Middle Attacks
ECDSA Authenticated R/W of Congurable
Memory
SHA-256 Compute Engine
FIPS 180 MAC for Secure Download/Boot
Operations
FIPS 198 HMAC for Bidirectional Authentication
and Optional GPIO Control
Two GPIO Pins with Optional Authentication Control
Open-Drain, 4mA/0.4V
Optional SHA-256 or ECDSA Authenticated On/O
and State Read
Optional Set On/O after Multiblock Hash for
Secure Boot/Download
RNG with NIST SP 800-90B Compliant Entropy
Source with Function to Read Out
Optional Chip Generated Pr/Pu Key Pairs for ECC
Operations
17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
8Kbits of EEPROM for User Data, Keys, and
Certificates
Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
Optional Input Data Component to Crypto and Key
Operations
Single-Contact 1-Wire Interface Communication with
Host at 11.7kbps and 62.5kbps
Operating Range: 3.3V ±10%, -40°C to +85°C
6-Pin TDFN-EP Package (3mm x 3mm)
Ordering Information and Typical Application Circuit appear
at end of data sheet.
19-100170; Rev 1; 10/17
1-Wire and DeepCover are registered trademarks of Maxim
Integrated Products, Inc.
Request Security User Guide and Developer Software ›
DS28E36 DeepCover Secure Authenticator
EVALUATION KIT AVAILABLE
Voltage Range on Any Pin Relative to GND ..........-0.5V to 4.0V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ...................................................... +125°C
Storage Temperature Range ............................ -55°C to +125°C
Lead temperature (soldering, 10s) ..................................+300°C
Soldering Temperature (reflow) ...................................... +260°C
Limits are 100% production tested at T
A
= +25°C and T
A
= +85°C. Typical values are at T
A
= +25°C. Limits over the operating tem-
perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are
guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and
are not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage V
PUP
(Note 1) 2.97 3.3 3.63 V
1-Wire Pullup Resistance R
PUP
(Notes 1, 2) 300 1000
Input Capacitance C
IO
(Note 3) 0.1 + Cx nF
Capacitor External C
X
(Note 1) 399.5 470 540.5 nF
Input Load Current I
L
IO pin at V
PUP
6 250 µA
Computation Current I
SPU
During t
RM
, t
WM
, t
CMP
, t
VES
, t
GKP
or t
GES
(Note 20)
7.5 mA
Computation Voltage V
SPU
Voltage at IO pin during t
RM
, t
WM
, t
CMP
,
t
VES
, t
GKP
, or t
GES
(Note 20)
2.2 V
High-to-Low Switching
Threshold
V
TL
(Notes 4, 5, 6)
0.65 x
V
PUP
V
Input Low Voltage V
IL
(Note 7)
0.10 x
V
PUP
V
DS28E36 DeepCover Secure Authenticator
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Maxim Integrated
2
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
6 TDFN-EP
PACKAGE CODE T633+2
Outline Number 21-0137
Land Pattern Number 90-0058
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
JA
) 55ºC/W
Junction to Case (θ
JC
) 9ºC/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
JA
) 42ºC/W
Junction to Case (θ
JC
) 9ºC/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial
Package Information
Limits are 100% production tested at T
A
= +25°C and T
A
= +85°C. Typical values are at T
A
= +25°C. Limits over the operating tem-
perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are
guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and
are not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-to-High Switching
Threshold
V
TH
(Notes 4, 5, 8)
0.75 x
V
PUP
V
Switching Hysteresis V
HY
(Notes 4, 5, 9) 0.3 V
Output Low Voltage V
OL
I
OL
= 4mA (Note 10) 0.4 V
Recovery Time
(Notes 1, 11, 12)
t
REC
Standard speed, R
PUP
= 1000Ω 25
µs
Overdrive speed, R
PUP
= 1000Ω 10
Rising-Edge Hold-o Time
(Notes 4, 13)
t
REH
Applies to standard speed only 1 µs
Time Slot Duration (Notes 1, 14) t
SLOT
Standard speed 85
µs
Overdrive speed 16
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time
(Note 1)
t
RSTL
Standard speed 480 640
µs
Overdrive speed 48 80
Reset High Time (Notes 1, 15) t
RSTH
Standard speed 480
µs
Overdrive speed 48
Presence Detect Fall Time
(Notes 4, 16)
t
FPD
Standard speed 1.25
µs
Overdrive speed 0.15
Presence-Detect Sample Time
(Notes 1, 17)
t
MSP
Standard speed 65 75
µs
Overdrive speed 7 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 1, 18)
t
W0L
Standard speed 60 120
µs
Overdrive speed 6 16
Write-One Low Time
(Notes 1, 18)
t
W1L
Standard speed 0.25 15
µs
Overdrive speed 0.25 2
IO PIN: 1-Wire READ
Read Low Time
(Notes 1, 19)
t
RL
Standard speed 0.25 15 - δ
µs
Overdrive speed 0.25 2 - δ
Read Sample Time
(Notes 1, 19)
t
MSR
Standard speed t
RL
+ δ 15
µs
Overdrive speed t
RL
+ δ 2
PIOA AND PIOB PINS
Output Low PIOV
OL
PIOI
OL
= 4mA (Note 10) 0.4 V
Input Low PIOV
IL
-0.3
0.15 x
V
PUP
V
Input High PIOV
IH
0.7 x
V
PUP
V
PUP
+ 0.3
V
Leakage Current PIOI
L
-1 +1 µA
DS28E36 DeepCover Secure Authenticator
www.maximintegrated.com
Maxim Integrated
3
Electrical Characteristics (continued)

DS28E36Q+U

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Security ICs / Authentication ICs DeepCover Secure Authenticator 1-WIRE
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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