1-Wire Signaling and Timing
The DS28E36 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E36 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E36 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
PUP
below the threshold V
TL
. To get
from active to idle, the voltage needs to rise from V
ILMAX
past the threshold V
TH
. The time it takes for the voltage
to make this rise is seen in Figure 6 as ε, and its dura-
tion depends on the pullup resistor (R
PUP
) used and the
capacitance of the 1-Wire network attached. The voltage
V
ILMAX
is relevant for the DS28E36 when determining a
logical level, not triggering any events.
Figure 5 shows the initialization sequence required to
begin any communication with the DS28E36. A reset pulse
followed by a presence pulse indicates that the DS28E36
is ready to receive data, given the correct ROM and
memory function command. If the bus master uses slew-
rate control on the falling edge, it must pull down the line
for t
RSTL
+ t
F
to compensate for the edge. A t
RSTL
dura-
tion of 480μs or longer exits the overdrive mode, returning
the device to standard speed. If the DS28E36 is in over-
drive mode and t
RSTL
is no longer than 80μs, the device
remains in overdrive mode. If the device is in overdrive
mode and t
RSTL
is between 80μs and 480μs, the device
resets, but the communication speed is undetermined.
After the bus master has released the line, it goes into
receive mode. Now, the 1-Wire bus is pulled to V
PUP
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. Now, the 1-Wire
bus is pulled to V
PUP
through the pullup resistor. When
the threshold V
TH
is crossed, the DS28E36 waits and
then transmits a presence pulse by pulling the line low. To
detect a presence pulse, the master must test the logical
state of the 1-Wire line at t
MSP
.
Immediately after t
RSTH
has expired, the DS28E36 is
ready for data communication. In a mixed population net-
work, t
RSTH
should be extended to a minimum 480μs at
standard speed and a 48μs at overdrive speed to accom-
modate other 1-Wire devices.
Read/Write Time Slots
Data communication with the DS28E36 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 6 illustrates the
definitions of the write and read time slots.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold V
TL
, the DS28E36 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Figure 5. Initialization Procedure: Reset and Presence Pulse
t
F
t
RSTL
t
REC
t
RSTH
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
MSP
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
RESISTOR (R
PUP
)
MASTER 1-WIRE SLAVE
DS28E36 DeepCover Secure Authenticator
www.maximintegrated.com
Maxim Integrated
│
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