DS28E36Q+U Datasheet DS28E36Q+T, DS28E36Q+U | P4-P6

Note 1: System requirement.

Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 3: Value represents the internal parasite capacitance when V

PUP

is first applied. Once the parasite capacitance is charged, it does

not affect normal communication. Typically, during normal communication, the internal parasite capacitance is effectively ~100pF.

Note 4: Guaranteed by design and/or characterization only. Not production tested.

Note 5: V

, V

, and V

are a function of the internal supply voltage, which is a function of V

PUP

, R

PUP

, 1-Wire timing, and

capacitive loading on IO. Lower V

PUP

, higher R

PUP

, shorter t

REC

, and heavier capacitive loading all lead to lower values of

, V

, and V

Note 6: Voltage below which, during a falling edge on IO, a logic-zero is detected.

Note 7: The voltage on IO must be less than or equal to V

ILMAX

at all times the master is driving IO to a logic-zero level.

Note 8: Voltage above which, during a rising edge on IO, a logic-one is detected.

Note 9: After V

is crossed during a rising edge on IO, the voltage on IO must drop by at least V

to be detected as logic-zero.

Note 10: The I-V characteristic is linear for voltages less than 1V.

Note 11: Applies to a single device attached to a 1-Wire line.

Note 12: t

REC

min covers operation at worst-case temperature V

PUP

, R

PUP

, C

, t

RSTL

, t

WOL

, and t

. t

RECMIN

can be significantly

reduced under less extreme conditions. Contact the factory for more information.

Note 13: The earliest recognition of a negative edge is possible at t

REH

after V

has been previously reached.

Note 14: Defines maximum possible bit rate. Equal to 1/(t

W0LMIN

+ t

RECMIN

Note 15: An additional reset of communication sequence sequence cannot begin until the reset high time has expired.

Note 16: Time from V

(IO)

= 80% of V

PUP

and V

(IO)

= 20% of V

PUP

at the negative edge on IO at the beginning of the Presence

Detect pulse.

Note 17: Interval after t

RSTL

during which a bus master can read a logic 0 on IO if there is a DS28E36 present.

Note 18: ε in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V

to V

Note 19: δ in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V

to the input-high

threshold of the bus master.

Note 20: I

SPU

is the current drawn from IO during a strong pullup (SPU) operation. The pullup circuit on IO during the SPU operation

should be such that the voltage at IO is greater than or equal to V

SPUMIN

. A low-impedance bypass of R

PUP

activated

during the SPU operation is the recommended way to meet this requirement.

Note 21: Write-cycle endurance is tested in compliance with JESD47H.

Note 22: Data retention is tested in compliance with JESD47H.

Note 23: 1-Wire communication should not take place for at least t

OSCWUP

after V

PUP

reaches V

PUP

min.

Limits are 100% production tested at T

= +25°C and T

= +85°C. Typical values are at T

= +25°C. Limits over the operating tem-

perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are

guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and

are not production tested.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STRONG PULLUP OPERATION

Generate ECDSA Signature Time t

GES

(Note 1) 50 ms

Generate ECC Key Pair t

GKP

(Note 1) 100 ms

Verify ECDSA Signature or

Compute ECDH Time

VES

(Note 1) 150 ms

Computation Time (HMAC or RNG) t

CMP

(Note 1) 3 ms

EEPROM

Read Memory Time t

(Note 1) 1 ms

Write Memory Time t

(Note 1) 15 ms

Write/Erase Cycles (Endurance) N

(Note 21) 100k —

Data Retention t

= +85°C (Note 22) 10 Years

POWER-UP

Power-Up Time t

OSCWUP

(Notes 1, 23) 2 ms

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Electrical Characteristics (continued)

Detailed Description

The DS28E36 is a secure authenticator that supports

multiple asymmetric (ECC-P256) and symmetric (SHA-

256) security functions. In addition to the security services

provided by the hardware implemented ECC and SHA-

256 engines, the device integrates a FIPS/NIST true ran-

dom number generator (RNG), 8Kb of secured EEPROM,

a decrement-only counter, two pins of configurable GPIO,

and a unique 64-bit serial number. The ECC public/private

key capabilities operate from the NIST defined P-256

curve and include FIPS 186 compliant ECDSA signature

generation and verification for bidirectional asymmetric

key authentication. Additionally, through FIPS/NIST 800-

56B ECDH-based key agreement, the device supports

secure storage and host communication of sensitive

data, such as application-specific crypto keys that would

be used independently by a host processor. The SHA-

256 secret-key capabilities are compliant with FIPS 180

and are flexibly used either in conjunction with ECDSA

operations or independently for multiple MAC and HMAC

functions. Through the integrated RNG, the device further

enhances system crypto functionality with the ability to

supply FIPS-grade random numbers to a host processor

along with internal-only functions including nonce values

for ECDSA operation and optional generation of its ECC

private keys. Two pins of GPIO can be independently

operated under command control and include configu-

rability supporting authenticated and nonauthenticated

operation including an ECDSA-based crypto-robust mode

to support secure-boot of a host processor.

The DS28E36 integrates an 8Kb secured EEPROM array

to store keys, certificates, general-purpose data and

control registers. Multiple user-programmable protec-

tion modes exist for the general-purpose memory space

including open, ECDSA R/W authentication protection,

SHA-256 HMAC R/W authentication protected, and SHA-

256 one-time-pad (OTP) R/W encryption in conjunction

with an ECDH established key. With these options, gen-

eral-purpose memory can be flexibly configured to store

end application data ranging from nonsensitive calibration

constants to critically sensitive host-system crypto keys.

The DS28E36 also provides a dedicated 17-bit counter

that operates in a decrement-only mode to support appli-

cations where limited use requirements exist and must be

tracked. Once set and upon command, the device decre-

ments the counter value by 1. After the counter reaches a

value of 0, no additional changes are possible. To prevent

reply attacks, a read of the counter is performed with user-

selectable ECDSA or SHA-256 HMAC authentication.

The block diagram in Figure 1 shows the relationships

between the circuit elements of the DS28E36.

PIN NAME FUNCTION

1 N.C. No Connection

2 IO 1-Wire IO

3 GND Ground

4 PIOB General-Purpose IO

5 PIOA General-Purpose IO

6 CEXT Input for External Capacitor

— EP

Exposed Pad (TDFN Only). Solder

evenly to the board’s ground plane for

proper operation. Refer to Application

Note 3273: Exposed Pads: A Brief

Introduction for additional information.

N.C.

GND

6 CEXT

PIOA

PIOB

TDFN-EP

(3mm x 3mm)

TOP VIEW

DS28E36

*EP

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Pin Conguration Pin Description

Design Resource Overview

Operation of the DS28E36 involves use of device

EEPROM and execution of device function commands.

The following provides an overview including the dec-

rement counter and GPIO pins. Refer to the DS28E36

Security Guide for full details.

Memory

A secured 8kbit EEPROM array is divided into two 4kbit

regions. One 4kbit space for user-programmable and

configurable memory, the other 4kbit space for registers

including ECC and SHA-256 keys, the decrement-only

counter, and programmable device control functions.

Depending on the register function, there are either

default or user-programmable protection modes.

Function Commands

After a 1-Wire Reset/Presence cycle and ROM function

command sequence is successful, a device function com-

mand can be accepted. These commands, in general,

follow the state flow diagrams of Figure 2 and Figure 3.

Within these flow diagrams, the data transfer is verified

when writing and reading by a CRC of 16-bit type (CRC-

16). The CRC-16 is computed as described in Maxim’s

Application Note 27.

Decrement Counter

The 17-bit decrement only counter can be written/initial-

ized one time. If unwritten, it reads as random data and

cannot be authenticated with a read. A dedicated device

function command is used to decrement the count value

by one with each call. Once the count value reaches a

value of 0, no additional decrements are possible.

GPIO Control

State setting and/or reads of the two open-drain GPIO

pins is controlled in accordance with user-programmable

protection settings. Multiple protection options exist based

on ECDSA, ECDH key establishment, or SHA256-HMAC.

Figure 1. Simplified Block Diagram

1-Wire FUNCTION

CONTROL

And

COMMAND

AUTHENTICATED

GPIO

64-BIT ROM ID

BUFFER

RNG

USER MEMORY

KEYS

DECREMENT COUNTER

ECC (256)

SHA-256

COMPUTE

CONTROL

PIOA

PIOB

Cext

DS28E36

PARASITE

POWER

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DS28E36Q+U

Mfr. #:

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Security ICs / Authentication ICs DeepCover Secure Authenticator 1-WIRE

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