Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V
TH
threshold before the write-
one low time t
W1LMAX
is expired. For a write-zero time
slot, the voltage on the data line must stay below the V
TH
threshold until the write-zero low time t
W0LMIN
is expired.
For the most reliable communication, the voltage on the
data line should not exceed V
ILMAX
during the entire
t
W0L
or t
W1L
window. After the V
TH
threshold has been
crossed, the DS28E36 needs a recovery time t
REC
before
it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
until
the read low time t
RL
is expired. During the t
RL
window,
when responding with a 0, the DS28E36 starts pulling
the data line low; its internal timing generator determines
when this pulldown ends and the voltage starts rising
again. When responding with a 1, the DS28E36 does not
hold the data line low at all, and the voltage starts rising
as soon as t
RL
is over.
The sum of t
RL
+ δ (rise time) on one side and the internal
timing generator of the DS28E36 on the other side define
the master sampling window (t
MSRMIN
to t
MSRMAX
), in
which the master must perform a read from the data line.
For the most reliable communication, t
RL
should be as
short as permissible, and the master should read close
to but no later than t
MSRMAX
. After reading from the data
line, the master must wait until t
SLOT
is expired. This
guarantees sufficient recovery time t
REC
for the DS28E36
to get ready for the next time slot. Note that t
REC
speci-
fied herein applies only to a single DS28E36 attached to a
1-Wire line. For multidevice configurations, t
REC
must be
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E36 supports. All ROM function commands are 8
bits long. A list of these commands follows (see the flow-
chart in Figure 7-1 and Figure 7-2).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E36’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E36 on a multidrop bus. Only the DS28E36 that
exactly matches the 64-bit ROM sequence responds to
the subsequent memory function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
DS28E36 DeepCover Secure Authenticator
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