LC75829PEH-H Datasheet LC75829PW-H, LC75829PEH-TLA-H, LC75829PEH-H | P19-P21

LC75829PE, LC75829PW

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19

Output waveforms (1/3-Duty 1/3-Bias Drive Scheme)

Control data Frame frequency fo[Hz]

FC0 FC1 FC2

Internal oscillator operating mode

(The control data OC is 0,

fosc=300[kHz]typ)

External clock operating mode

(The control data OC is 1

and EXF is 0, f

CK

1=300[kHz]typ)

External clock operating mode

(The control data OC is 1

and EXF is 1, f

CK

2=38[kHz]typ)

0 0 0 fosc/6144 f

CK

1/6144 f

CK

2/768

0 0 1 fosc/4608 f

CK

1/4608 f

CK

2/576

0 1 0 fosc/3072 f

CK

1/3072 f

CK

2/384

0 1 1 fosc/2304 f

CK

1/2304 f

CK

2/288

1 0 0 fosc/1536 f

CK

1/1536 f

CK

2/192

1 0 1 fosc/1152 f

CK

1/1152 f

CK

2/144

1 1 0 fosc/768 f

CK

1/768 f

CK

2/96

Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the

(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, f

CK

1/3072, f

CK

2/384).

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

V

DD

0V

V

DD

2

V

DD

1

0V

fo

[

Hz

]

V

DD

COM3

COM2

COM1

LCD driver output when all LCD segments

corresponding to COM1, COM2, and COM3

are on.

LCD driver output when LCD segments

corresponding to COM2 and COM3 are on.

LCD driver output when LCD segments

corresponding to COM1 and COM3 are on.

LCD driver output when only LCD segments

corresponding to COM1 are on.

LCD driver output when only LCD segments

corresponding to COM2 are on.

LCD driver output when only LCD segments

corresponding to COM3 are on.

LCD driver output when LCD segments

corresponding to COM1 and COM2 are on.

LCD driver output when all LCD segments

corresponding to COM1, COM2, and COM3

are off.

LC75829PE, LC75829PW

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20

Display Control and the

INH

Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to

D159 and the control data) is undefined when power is first applied, applications should set the INH

pin low at the same

time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S50, COM1 to COM3, COM4/S51,

S52, and S53/OSCI pins to the VSS level.) and during this period send serial data from the controller. The controller

should then set the INH

pin high after the data transfer has completed. This procedure prevents meaningless display at

power on.

(See Figure 5 and Figure 6.)

• 1/4 duty

• 1/3 duty

Notes: t11ms

t20

tc…10s min

Display data and control

data transferred

V

DD

t2

D1 to D52,PS10,PS11,

EXF,P0 to P2,DT,DN,

FC0 to FC2,OC,SC,BU

Internal data (D53 to D104)

Internal data (D105 to D152)

Undefined

CE

INH

Undefined

Defined

[Figure 5]

Undefined

V

IL

1

tc

V

IL

1

Internal data (D153 to D208)

Internal data

t1

Defined

Undefined

Display data and control

data transferred

V

DD

t2

D1 to D54,PS10,PS11,

EXF,P0 to P2,DT,DN,

FC0 to FC2,OC,SC,BU

Internal data (D55 to D108)

Internal data (D109 to D159)

CE

INH

Undefined

[Figure 6]

Undefined

V

IL

1

tc

V

IL

1

Internal data

t1

Undefined

Defined

Undefined

Notes: t11ms

t20

tc…10s min

LC75829PE, LC75829PW

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21

Notes on Controller Transfer of Display Data

When using the LC75829 in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and in 1/3

duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer all of

the display data within 30 ms to maintain the quality of displayed image.

S53/OSCI Pin Peripheral Circuit

(1) Internal oscillator operating mode (control data OC = 0)

Connect the S53/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.

(2) External clock operating mode (control data OC = 1)

When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22 k) between

the S53/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according

to the allowable current value at the external clock output pin. Also make sure that the waveform of the external

clock is not heavily distorted.

(3) Unused pin treatment

When the S53/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0)

to keep the pin open.

OSCI/S53 External clock output pin

Rg

External oscillator

Note: Allowable current value at external clock output pin 

V

DD

Rg

OSCI/S53

To LCD panel

OSCI/S53

OPEN

LC75829PEH-H

LC75829PEH-H

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