LTC6820
3
6820fb
For more information www.linear.com/LTC6820
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 2.7V to 5.5V, V
DDS
= 1.7V to 5.5V, R
BIAS
= 2k to 20k unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
DD
Operating Supply Voltage Range
l
2.7 5.5 V
V
DDS
IO Supply Voltage Range (Level Shifting) Affects CS, SCK, MOSI, MISO and EN Pins
l
1.7 5.5 V
I
DD
Supply Current, READY/ACTIVE States
(Note 4)
R
BIAS
= 2kΩ (I
B
= 1mA) 1/t
CLK
= 0MHz
1/t
CLK
= 1MHz
l
4 4.8
7
5.8 mA
mA
R
BIAS
= 20kΩ (I
B
= 0.1mA) 1/t
CLK
= 0MHz
1/t
CLK
= 1MHz
l
1.3 2
2.4
2.9 mA
mA
Supply Current, IDLE State MSTR = 0V
MSTR = V
DD
l
l
2
1
6
3
µA
µA
I
DDS
IO Supply Current (Note 5) SPI Inputs and EN Pin at 0V or V
DDS
,
SPI Outputs Unloaded
l
1 µA
Biasing
V
BIAS
Voltage on IBIAS Pin READY/ACTIVE State
IDLE State
l
1.9 2.0
0
2.1 V
V
I
B
Isolated Interface Bias Current (Note 6) R
BIAS
= 2k to 20k
l
V
BIAS
/R
BIAS
mA
A
IB
Isolated Interface Current Gain V
A
≤ 1.6V I
B
= 1mA
I
B
= 0.1mA
l
l
18
18
20
20
22
24
mA/mA
mA/mA
V
A
Transmitter Pulse Amplitude V
A
= |V
IP
– V
IM
| V
DD
< 3.3V
V
DD
≥ 3.3V
l
l
V
DD
– 1.7V
1.6
V
V
V
ICMP
Threshold-Setting Voltage on ICMP Pin V
TCMP
= A
TCMP
• V
ICMP
l
0.2 1.5 V
I
LEAK(ICMP)
Leakage Current on ICMP Pin V
ICMP
= 0V to V
DD
l
±1 µA
I
LEAK(IP/IM)
Leakage Current on IP and IM Pins IDLE State, V
IP
= V
IM
= 0V to V
DD
l
±2 µA
A
TCMP
Receiver Comparator Threshold Voltage
Gain
V
CM
= V
DD
/2 to V
DD
– 0.2V,
V
ICMP
= 0.2V to 1.5V
l
0.4 0.5 0.6 V/V
V
CM
Receiver Common Mode Bias IP/IM Not Driving (V
DD
– V
ICMP
/3 – 167mV) V
R
IN
Receiver Input Resistance Single-Ended to IP or IM
l
26 35 42 kΩ
Idle/Wake-Up (See Figures 13, 14, 15)
V
WAKE
Differential Wake-Up Voltage
(See Figure 13)
t
DWELL
= 240ns
l
240 mV
t
DWELL
Dwell Time at V
WAKE
V
WAKE
= 240mV
l
240 ns
t
READY
Start-Up Time After Wake Detection
l
8 µs
t
IDLE
Idle Time-Out Duration
l
4 5.7 7.5 ms
Digital I/O
V
IH(CFG)
Digital Voltage Input High, Configuration
Pins (PHA, POL, MSTR, SLOW)
V
DD
= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)
l
0.7 • V
DD
V
V
IL(CFG)
Digital Voltage Input Low, Configuration
Pins (PHA, POL, MSTR, SLOW)
V
DD
= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)
l
0.3 • V
DD
V
V
IH(SPI)
Digital Voltage Input High, SPI Pins
(CS, SCK, MOSI, MISO)
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
l
l
0.7 • V
DDS
0.8 • V
DDS
V
V
V
IL(SPI)
Digital Voltage Input Low, SPI Pins
(CS, SCK, MOSI, MISO)
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
l
l
0.3 • V
DDS
0.2 • V
DDS
V
V
V
IH(EN)
Digital Voltage Input High, EN Pin V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
l
l
2
0.85 • V
DDS
V
V
V
IL(EN)
Digital Voltage Input Low, EN Pin V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
l
l
0.8
0.25 • V
DDS
V
V
V
OH
Digital Voltage Output High (CS and SCK) V
DDS
= 3.3V, Sourcing 2mA
V
DDS
= 1.7V, Sourcing 1mA
l
l
V
DDS
– 0.2
V
DDS
– 0.25
V
V
V
OL
Digital Voltage Output Low
(MOSI, MISO, CS, SCK)
V
DDS
= 3.3V, Sinking 3.3mA
V
DDS
= 1.7V, Sinking 1mA
l
l
0.2
0.2
V
V
